JPS6388919A - Odd number frequency dividing circuit - Google Patents

Abstract

PURPOSE:To output an odd number frequency dividing clock corresponding to an inputted select signal and coincident with the leading edge by adding the output of an odd number frequency division means and an output via a D type flip-flog inputted with an inverted clock to a selector means. CONSTITUTION:An odd number frequency dividing clock from an odd number frequency division means 1 and a clock shifting the odd number frequency division clock by using the inverted phase clock of a D FF 5 are fed to a selector means 6. The means 6 selects odd frequency clocks having a minimum duty factor and different phase corresponding to the select signal to take OR. Then the trailing is shifted by a half bit each to obtain odd number frequency division with different duty factor. Thus, odd number frequency clocks corresponding to the inputted select signal and coincident with the leading edge are obtained.

Description

[Detailed Description of the Invention] [Summary] In an odd number frequency dividing circuit, an odd number divided clock obtained by dividing an input clock by an odd number and an antiphase clock are used to shift the odd number divided clock by half a pit. By selecting these and calculating the logical sum, it is possible to obtain divided clocks with different duty factors that have the same rising edge, and to make them suitable for LSI implementation.

[Industrial application field]

The present invention relates to an improvement in an odd frequency divider circuit.

Generally, if a clock is divided by 3 using a divide-by-3 circuit, the duty factor will be 1/3. In the case of a divide-by-5 circuit, the duty factor is 215, but this is used, for example, to test the operating margin of a logic circuit.

It is sometimes required to be able to switch the duty factor of the clock output from the divide-by-3 circuit into three stages: approximately 33.3%, 50χ, and 66.6%.

On the other hand, in recent years, in response to the miniaturization of devices, circuits have been made into LSIs, so it is necessary that the odd frequency divider circuit also have a circuit configuration suitable for LSIs.

[Conventional technology]

FIG. 4 is a block diagram of the conventional example, and FIG. 5 is a time chart of FIG. 4, and the numbers on the left side of FIG. 5 indicate the time charts of the portions with the same numbers in FIG. The operation of FIG. 4 will be described below with reference to FIG. 5 in the case where the input clock is frequency-divided by three.

-Flip-flop (hereinafter abbreviated as D-FP) 11
If terminal Q of ゜12 is set to L, then D-FF
H is added to the terminal 11 as shown in Figure 5-■,
This H is input at the rising edge of the clock shown in FIG. 5-2, and the terminal Q changes to H, and returns to L at the next rising edge of the clock (see the first half of FIG. 5-2).

Therefore, as shown in the first half of Figure 5-■, the terminal Q of the D-FF 12 changes from L to H with a delay of 1 bit from the D-FF 11, and then returns to the high state. returns to the initial state H at point A in Figure 5-■ and returns to D-F.
FII and 12 repeat the above operation as indicated by the dotted arrows.

Then, the output of the terminal Q of the D-FP 12 (a 3-frequency divided clock with a duty factor of 173) is delayed by half a bit by the delay line 2, for example, and then sent to the set-reset flip-flop (hereinafter abbreviated as R3-FP) 3. (See Figure 5-■).

Since the output of the terminal Q of the D-FF 11 is applied to the terminal S of this R5-FF, it is set by the output of the D-FP 11 and reset by the output of the delay line 2, as shown in Fig. 5-■. The NOR circuit 4 is a clock divided by 3 with a duty factor of 50χ shown in 3, which has a duty factor of approximately 50χ.
When the select signal S2 becomes L, the duty factor becomes approximately 33.3z (50χ-%
When the selector signal S of the frequency-divided clock (bit) becomes L, the duty factor in Figure 5-0 becomes approximately 66.6.
The 3-divided clocks of χ (50χ+A bits) are outputted through NOR circuits 42, 43, and 44, respectively.

[Problem that the invention seeks to solve]

As explained above, the duty factor is approximately 50χ
Since a delay line or gates connected in multiple stages is used as a half-bit shift portion for the purpose of achieving this, a large space is required, or the amount of delay may fall outside of the allowable range due to deviations in the characteristics of the elements.

Furthermore, in order to keep the duty factor constant when changing the clock frequency, the half-bit shift part must be readjusted, so it has to be made smaller.

The circuit must be suitable for LSI integration by reducing the number of adjustment points.

Furthermore, as shown in FIG. 5-2, when the duty factor is switched, the rising edge changes, resulting in two problems: jitter occurs.

[Means for solving problems]

FIG. 1 shows a diagram of the principle of the present invention. The output of the odd number frequency dividing means 1 and the output via the D type flip-flop 5 to which the anti-phase clock is input are applied to the selection means 6. The configuration is such that an odd-number frequency-divided clock corresponding to the input select signal is output from here.

[Effect]

In the present invention, the odd number frequency divided clock from the odd number frequency dividing means 1 and the half bit shifted version of this odd number frequency divided clock using a D type flip-flop 5 using an antiphase clock are added to the selection means 6.

The duty factor is the minimum in the selection means.

By selecting odd-numbered frequency-divided clocks with all different phases in accordance with the select signal and performing a logical sum, the falling part is shifted by half a bit to obtain odd-numbered frequency-divided clocks with different duty factors. Therefore, the rising edge does not change even if the duty factor changes.

Further, since a D-type flip-flop is used as the half-bit shifting means and no delay line or multi-stage connected gates are used, the circuit can be miniaturized and the number of adjustment parts can be reduced, making it suitable for LSI implementation.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a time chart of FIG. 2. Also, D-FF 11°12,
The NOR circuit 13 corresponds to the odd frequency dividing means 1, and the NOR circuits 61 to 64 correspond to the selection means 6.

Incidentally, the same reference numerals refer to the same objects throughout the plan, and the numbers on the left side of FIG. 3 indicate the time charts of the numbers in FIG. 2.

The operation of FIG. 2 will be described below with reference to FIG. 3, taking as an example the case where the input clock frequency is divided by three.

First, the operation of the odd frequency dividing means 1, which is composed of the D-FF 11.12 and the NOR circuit 13, is as described above and in FIG.

As shown by the dotted line arrow (2), the duty factor 1/3 divided by 3 clock shifted by 1 bit is used as D-FF 1.
It is output from terminal Q of 1 and upper 2.

Therefore, the output of the terminal Q of the D-FF 11- is connected to the NOR circuit 6.
1, and in addition to the D-FF 51, a half-bit shifted signal using an anti-phase clock is added to the NOR circuit 62. Furthermore, the output of the terminal Q of the D-FF 12 is added to the NOR circuit 63, and the NOR circuit 6 is
Turn on/off 1 to 63.

That is, as shown in Figure 3-■, 31 is set to L and SZ+33
When set to H, a 3-frequency divided clock with a duty factor of 173 becomes S, and when s3 is set to H with S and 82 set to H, D-F
The OR circuit 64 is the logical sum of the outputs of terminal Q of F 11 and 51.
The 3-frequency divided clock with a duty factor of 172 is taken by S + "' When S 3 is set to L, D-FF 1
A 3-divided clock with a duty factor of 273 is obtained by ORing the outputs of the terminal Q of 1.12.51, but since the rising edges all match, there is no jitter even if the duty factor is switched. Does not occur.

In addition, in order to shift half a bit, an anti-phase clock and one D-PF are used instead of delay lines and gates connected in multiple stages, so the space is small and the deviation in characteristics is small. Furthermore, since there is no need for adjustment even if the clock frequency is changed, this odd number frequency dividing circuit is suitable for LSI implementation.

〔Effect of the invention〕

As described in detail above, the present invention has the advantage that it is possible to obtain an odd number frequency dividing circuit suitable for LSI, and also to obtain a frequency divided clock whose rising edges coincide with each other.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a time chart of Fig. 2, Fig. 4 is a block diagram of a conventional example, and Fig. 5 is a block diagram of an embodiment of the present invention. The time chart in Figure 4 is shown. In the figure, 1 is an odd frequency dividing means, 5 is a D type flip-flop, and 6 is a selecting means. 10 1 ・

Claims (1)

[Claims] Odd frequency dividing means (1) for dividing an input clock by an odd number; and a D type flip-flop (5) for shifting the output of the odd frequency dividing means by half a bit using an anti-phase clock whose phase is inverted with respect to the input clock. ), and select means (6) for selecting the output of the odd frequency dividing circuit and the output of the half-bit shifting means using an external selection signal and calculating a logical sum. .