JPH04273715A - Counter circuit - Google Patents

Abstract

PURPOSE:To freely set the phase of an output signal in a counter circuit which generates a required timing signal by frequency-dividing an input signal. CONSTITUTION:A frequency division circuit 13 is comprised of four D flip-flop circuits 14-17, and outputs a signal inputted to an input terminal 11 by performing quadripartite frequency division. A decoder 19 outputs a phase signal based on phase data outputted from a phase setting data generating part 18. A comparator 20 compares the combination of the output signals of the flip-flop circuits 14-17 inputted to the input terminals at one side of EXOR gates 21-24 with that of the phase signal outputted from the decoder 19, and outputs a signal of phase in accordance with the phase data outputted from the phase setting data generating part 18.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a counter circuit that generates signals used for operating timing of various circuits.
In particular, the present invention relates to a counter circuit having a function of changing the phase of an output signal.

0002

2. Description of the Related Art Conventionally, a counter circuit of this type has a plurality of, for example four, D-type flip-flop (F/F) circuits 3 to 3 between an input terminal 1 and an output terminal 2, as shown in FIG. 6. The input terminal 1 is connected to the C terminal of a flip-flop circuit 3, and the inverted Q terminal of this flip-flop circuit 3 is connected to the D terminal of the flip-flop circuit 3. Q of flip-flop circuit 3
The terminal is connected to the C terminal of the next-stage flip-flop circuit 4. Thereafter, the configuration is similar, and the Q terminal of the last flip-flop circuit 6 is connected to the output terminal 2.

That is, in this counter circuit, a signal inputted to an input terminal 1 is frequency-divided by flip-flop circuits 3 to 6, and output as a timing signal from an output terminal 2. The numbers were set according to the timing.

0004

As described above, in the conventional counter circuit, a desired timing signal is obtained by changing the number of flip-flop circuits. That is,
In conventional counter circuits, the phase of the output signal is defined by the input signal and the circuit, and the phase cannot be set freely.

However, in general, after a circuit is assembled, factors that cannot be predicted at the circuit design stage occur, such as a deviation in the length of the printed circuit board wiring or a deviation in the mounting position, resulting in a phase shift in the output signal. There are cases. When the phase is shifted in this way, it is not possible to change the phase of the output signal back and forth unless the phase of the input signal is changed. Therefore, in order to obtain a timing signal with the required phase, it is currently necessary to review the circuit.

The present invention has been made in view of the above problems, and its purpose is to change the phase of the output signal to an appropriate value even if the phase is shifted due to factors that cannot be predicted at the circuit design stage. An object of the present invention is to provide a counter circuit that can eliminate the need to review the circuit.

[0007]

[Means for Solving the Problems] In order to solve the above problems, the counter circuit of the present invention includes a frequency dividing means for dividing an input signal, a phase setting data generating means for generating phase setting data, and a phase setting data generating means for generating phase setting data. A decoder receives as input the phase data generated by the setting data generating means and outputs a phase signal, and compares the output signal of the frequency dividing means with the output signal of the decoder, and calculates the phase data generated by the phase setting data generating means. and comparing means for outputting a signal having a corresponding phase.

[0008] The frequency dividing means is specifically constituted by a plurality of flip-flop circuits, and the comparison means has one input terminal each inputting each output signal of the plurality of flip-flop circuits, and the other input terminal. It is composed of a plurality of exclusive OR gates to which input terminals are input the phase signals output from the decoder, and an OR gate to which the output signals of these gates are input.

With such a configuration, the counter circuit of the present invention can make the phase of the output timing signal variable, and even if the phase is shifted due to factors that cannot be predicted at the circuit design stage, the timing signal remains unchanged. The phase can be changed to an appropriate value, eliminating the need to review the circuit.

0010

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a counter circuit according to an embodiment of the present invention. In this counter circuit, a frequency dividing circuit 13 is provided between the input terminal 11 and the output terminal 12.
and a comparison circuit 20 are provided. The frequency dividing circuit 13 is composed of four, for example, D-type flip-flop circuits 14 to 17, similar to a conventional counter circuit, and divides the frequency of the signal input to the input terminal 11 by four and outputs the divided signal. . These output signals are set by the phase of the input signal input from the input terminal 11 as described above.

The comparison circuit 20 is composed of four exclusive OR gates 21-24 and an OR gate 25 which receives the output signals of these gates 21-24. The output signals of the respective Q terminals of the flip-flop circuits 14 to 17 are input to one input terminal of each of the exclusive OR gates 21 to 24, respectively. That is,
Signals whose phases are shifted one pulse at a time are sequentially input to these exclusive OR gates 21 to 24. Further, an output signal from the decoder 19 is input to the other input terminal of each of these exclusive OR gates 21 to 24. The decoder 19 inputs the phase data output from the phase setting data generator 18, decodes it, and outputs a phase signal of "1" or "0".
” signal. Phase setting data generator 1
Reference numeral 8 is composed of a CPU (central processing unit), which outputs phase data to the decoder 19 based on input from an operation section (not shown).

The comparison circuit 20 includes an exclusive OR gate 21
The combination of the output signals of the flip-flop circuits 14 to 17 inputted to one input terminal of the flip-flop circuits 14 to 24 is compared with the combination of phase signals output from the decoder 19, and when the combinations match, the output level is determined. It changes. The output signal of this comparison circuit 20 is input to the D terminal of the flip-flop circuit 26. This flip-flop circuit 26 prevents the so-called whisker from occurring due to a slight timing difference between the output signals of the flip-flop circuits 14 to 17 and the phase signal output from the decoder 19. is configured to receive an input signal from an input terminal 11, and its Q terminal is connected to an output terminal 12. In addition,
Since the phase of the output signal is shifted by this amount due to the flip-flop circuit 26, it is necessary to generate data from the phase setting data generating section 18 that takes this into consideration.

Next, the operation of the counter circuit of this embodiment will be explained with reference to the timing chart shown in FIG. That is, first, when predetermined phase data is set, the phase setting data generator 18 outputs the phase setting data to the decoder 19. This data is decoded by the decoder 19 and input as phase signals f to i to the other input terminals of the exclusive OR gates 21 to 24 in the comparison circuit 20. Here, the phase signals f to i are, for example, high level "1", "1", low level "0", "0", respectively.
shall be. On the other hand, the input signal a input from the input terminal 11
are each flip-flop circuit 14 to 17 of frequency dividing circuit 13
are input sequentially. These flip-flop circuits 14~
17 output signals b to e whose phases are shifted by one pulse from each other. These signals are each input to one input terminal of exclusive OR gates 21 to 24 in comparison circuit 20. The comparison circuit 20 compares the input signals b to e and the phase signals f to i, and when they match, determines the phase, and the OR gate 25 outputs the signal j. This signal j is input to the D terminal of the flip-flop circuit 26, and in this flip-flop circuit 26 it becomes a signal k having the phase set by the phase setting data generating section 18, which is outputted from the output terminal 12 as a timing signal.

As described above, in the counter circuit of this embodiment,
The phase of the output timing signal k can be changed based on the setting data from the phase setting data generating section 18. Therefore, even if the phase is shifted due to factors that cannot be predicted at the circuit design stage, the phase of the timing signal k can be changed to an appropriate value, eliminating the need to review the circuit.

It should be noted that the present invention is not limited to the above embodiments, but can be modified in various ways without changing the gist thereof. For example, although the flip-flop circuit constituting the frequency dividing circuit 13 has been described as a D-type flip-flop circuit, it may be an RS (reset set) type flip-flop circuit.

As explained above, according to the counter circuit according to claims 1 and 2, a phase signal is generated based on the output of the frequency dividing means for frequency dividing the input signal and the phase data generated by the phase setting data generating means. Since the phase setting data generating means outputs a signal with a phase corresponding to the generated phase data, the phase of the output signal can be changed arbitrarily. Even if the phase shifts due to unpredictable factors, the phase of the timing signal can be changed to an appropriate value, eliminating the need to review the circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing a counter circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the counter circuit in FIG. 1;

FIG. 3 is a circuit configuration diagram showing a conventional counter circuit.

[Explanation of symbols]

11 Input terminal 12 Output terminal 13 Frequency divider circuit 14-17 Flip-flop circuit 18 Phase setting data generation section 19 Decoder 20 Comparison circuit 21-24 Exclusive OR gate 25 Logical sum gate 26 Flip-flop circuit

Claims (2)

[Claims] 1. A frequency dividing means for dividing an input signal, a phase setting data generating means for generating phase setting data, and a decoder receiving as input the phase data generated by the phase setting data generating means and outputting a phase signal. , further comprising comparing means for comparing the output signal of the frequency dividing means and the output signal of the decoder and outputting a signal having a phase corresponding to the phase data generated by the phase setting data generating means. counter circuit. 2. The frequency dividing means includes a plurality of flip-flop circuits, and the comparing means receives each output signal of the plurality of flip-flop circuits at one input terminal, and inputs each output signal from the plurality of flip-flop circuits at the other input terminal. 2. The counter circuit according to claim 1, comprising a plurality of exclusive OR gates to which the phase signals outputted from the decoder are input, and an OR gate to which the output signals of these gates are input.