JP2000307419A - Frequency dividing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the frequency dividing circuit which can divide the frequency of a reference clock at an arbitrary frequency-division ratio so that the obtained deviation in frequency-divided clock interval is less than one reference clock. SOLUTION: The frequency dividing circuit has an M (natural number)-ary adder 2 and a register 3, the adder 2 adds a constant value N (natural number) inputted to a Y input terminal by reference clocks and a value inputted from the register 3 to an X input terminal and the register 3 latches the addition value obtained by the adder 2 and outputs the value to the adder 2. The adder 2 outputs a frequency-divided clock from a carry signal CRY terminal when the addition value of the value N and latched value exceeds the constant value M. Therefore, an arbitrary frequency division ratio (N/M) can be obtained by varying the values N and M and fluctuations in frequency-divided clock interval is reduced to less than one reference clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency dividing circuit having a simple structure which can divide a reference clock at an arbitrary frequency dividing ratio and reduce the variation in the interval of the obtained divided clock as compared with the prior art. is there.

[0002]

2. Description of the Related Art In general, as a frequency dividing circuit, a rate multiplexer and an N frequency dividing counter are known. Figures 3 and 4
2 shows a configuration of a conventional binary rate multiplexer and a timing chart of a frequency dividing operation.

As shown in these drawings, a frequency dividing circuit (rate multiplexer) 43 has a binary counter 31 composed of four T-flip-flops. The reference clock to be counted up. The output of the binary counter 31 and the inverted output are output to the AND-OR circuit 34. AN
The output signal of the D-OR circuit 34 becomes the output shown in FIG. 4 according to the frequency division ratio control input value. This output signal, frequency dividing ratio control input value N to 1 cycle (2 ⁴ clocks) of the binary counter 31 (N 16 following values) is output as many times that match. This output signal is a frequency-divided clock.

[0004]

The frequency divider constructed as described above has the following problems.

That is, the rate multiplexer has a problem that the divided clock interval is not constant. For example, a state occurs in which the clock interval is not uniform in the case of the division ratio input 6 in FIG.

Conventionally, various methods have been proposed for keeping the frequency of the divided clock constant. However, any of these methods requires a plurality of circuit elements such as flip-flops, and the configuration is complicated. There is a problem that.

[0007] In view of the above, the object of the present invention is to provide:
An object of the present invention is to propose a frequency dividing circuit which can divide a clock at an arbitrary frequency dividing ratio, has a small deviation of the divided clock interval, and can be constituted by a small number of circuit elements.

[0008]

In order to solve the above-mentioned problems, a frequency dividing circuit according to the present invention comprises an adder of an M-ary number (M natural number) and an addition result of the adder every rising edge of a reference clock. A register to be latched, a predetermined value N (N natural number) is input to a first input terminal of the adder, and the latch content of the register is input to a second input terminal of the adder. A frequency-divided clock obtained by dividing the reference clock by N / M is output from a carry signal output terminal of the frame.

The frequency dividing circuit thus configured can divide the clock at an arbitrary dividing ratio, and the fluctuation of the interval between the divided clocks can be made within one clock. Further, since only the adder and the register need be used as the circuit elements, the configuration is simplified.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A frequency divider according to the present invention will be described below with reference to the drawings.

(Overall Configuration) FIG. 1 is a block diagram showing a frequency dividing circuit of this embodiment, and FIG. 2 is a timing chart of the frequency dividing circuit.

As shown in FIG. 1, the frequency dividing circuit 1 comprises an adder 2 of an M-ary number (M is a natural number), in this example, a hexadecimal number, and a register 3. The adder 2 is connected to two buses 4 and 7. That is, the bus 4 is connected to the adder 2
The bus 7 is connected to the X terminal 10 of the adder 2.
It is connected to the. The adder 2 adds a value N (N is a natural number, which is “6” in this example) input to the Y terminal 9 via the bus 4 and a value input via the bus 7. , And outputs the addition result SUM to the bus 6.

The adder 2 determines that the added value SUM is "15" (=
M-1), a carry signal is output from the CRY terminal 12 to the output line 8 when a carry occurs. Each of the two input buses and one output bus of the hexadecimal adder has a 4-bit configuration.

The register 3 latches the added value SUM obtained by the adder 2 at the rising or falling edge of the clock. The sum SUM is input to the I terminal 14 of the register 3 via the bus 6. The latched value is input from the O terminal 15 of the register 3 to the X terminal 10 of the adder 2 via the bus 7.

(Dividing operation) Mainly referring to FIG.
Will be described. At the rise of the first clock, the output value of the O terminal 15 of the register 3 is set to “0”.

At the rising edge of the first clock, the value “6” is input to the Y terminal 9 of the adder 2, and the output value “0” of the register 3 is input to the X terminal 10. As a result,
The adder 2 adds the respective values and outputs a value “6” from the Z terminal 11 to the bus 6.

At the rise of two clocks, the register 3 latches the value “6” of the bus 6, the value “6” is input to the X terminal 10 of the adder 2 via the bus 7,
, A predetermined value “6” that is input every clock. Thereby, the adder 2 calculates the respective values “6”,
"6" is added, and the value "12" is output from the Z terminal 11 to the bus 6.

At the rise of three clocks, the register 3 latches the value “12” of the bus 6, the value “12” is input to the X terminal 10 of the adder 2 via the bus 7, and the value is “6” is input. Thereby, the adder 2
Adds the respective values and outputs a value "2" from the Z terminal 11 to the bus 6, and at the same time as this output, a carry signal, that is, a divided clock is output from the CRY terminal 12 to the output line 8. .

The value "2" is output from the Z terminal 11 to the bus 6 because the hexadecimal adder 2 adds "6" to "12" to become "18". But,
A value “2” obtained by subtracting “16” from “18” is the addition result of the adder 2. The carry signal is output because the sum of the value input to the X terminal 10 of the adder 2 and the value input to the Y terminal 9 becomes 15 or more.
That is, a carry signal is output when a carry occurs in a hexadecimal number.

The frequency divider 1 of this embodiment adds a certain value every clock, and outputs a carry signal when the value exceeds a certain value. That is, this carry signal is a frequency-divided clock. In this example, since N = 6 and M = 16, 16/6 = 2.6666..., A carry signal is output every two clocks or three clocks, and an average of 2.666. Each time, a frequency-divided clock is output. Thus, the frequency division ratio of this example is 6 /
16 (= N / M).

(Division accuracy) As described above, the frequency dividing circuit 1 of the present embodiment adds the value N for each clock, and when the value N exceeds the value M, the carry signal, that is, the divided clock is added. Output. Therefore, the timing at which the divided clock is output is determined by the divided value (M / N).
The division value (M / N) is a natural number or a value including a value below the decimal point. In both cases, it will be described that the difference between the divided clock intervals is less than one clock.

First, when the division value (M / N) is a natural number, this value M is a multiple of the value N (the value of M / N), and a carry occurs after a clock of the multiple value. The divided clock is output, and the timing at which the next divided clock is generated is also output after the value (M / N) clocks. Therefore, the divided clock interval is always constant.

Next, a case where the division value (M / N) is a value that is indivisible and includes a decimal point will be described. Value (M / N)
Is the sum of the natural number N1 and the decimal point P1. Therefore,
The timing at which the first divided clock is output is
After (N1 + 1) clocks. Because the value (M
/ N) is a value including a decimal point, the value of the value N × the value N1 is smaller than the value M, and the value of the value N × the value (N1 + 1) is the value M for the first time.
Because it exceeds. The value of the value N × the value (N1 + 1) is smaller than the value (M + N). This is the value ｛(M + N)
Since the value of {N} is (M / N + 1) and the value N1 is smaller than the value (M / N), the value of the value N × the value (N1 + 1) is the value N × the value (M / N + 1) = the value This is because the value is smaller than (M + N).

Therefore, the output from the adder 1 to the bus 6 at the time of the first carry becomes a value between 1 and the value (N-1). The next divided clock is output when the value N is added, and the added value again becomes equal to or greater than the value M in the adder 1.

As described above, since the output of the adder 1 is a value between 1 and the value (N-1), the difference up to the value M is from the value (M-1) to the value (M-N + 1). . When the difference up to the value M is the value (M-1), the value (M-1) /
N is a value (M / N-1 / N). If the decimal point of the value 1 / N is P2, the value (M / N-1 / N) = value (N1 + P1)
-P2). The integer part of the value (N1 + P1-P2) is
The value (N1-1) or the value N1 and then the addition value of the adder 1 exceeds the value M is that the value N is changed to N1 times or (N1 + 1).
It is the time when it is added twice.

The difference of the adder 1 up to the value M is the value (M-
N + 1), the value (M−N + 1) / N
Is the value (M / N-1 + 1 / N), and assuming that the decimal point of the value 1 / N is P2, the value (M / N-1 + 1 / N) = the value (N1
+ P1-1 + P2). Value (N1 + P1-1 + P
The integer part of 2) is the value (N1-1) or the value N1, and the next time the addition value of the adder 1 exceeds the value M is that the value N is N1 times.
Or when adding (N1 + 1) times.

Therefore, the addition result of the adder 1 exceeds the value M every time the value N is added N1 times or (N1 + 1) times. Therefore, the fluctuation of the interval between the divided clocks can be suppressed within one clock.

(Other Embodiments) In the above example, M = 16 and N = 6, but the present invention is not limited to these values. By changing these values, a frequency dividing circuit having an arbitrary frequency dividing ratio can be realized.

[0029]

As described above, the frequency dividing circuit of the present invention is composed of two circuit elements, an adder and a register.
The adder adds the constant value N input every time the reference clock is generated and the input value from the register. The register latches the added value obtained by the adder and outputs the value to the adder. Accordingly, the adder adds a certain value every time the reference clock is generated. When the addition result exceeds a certain value M, the adder outputs a carry signal as a divided clock.

According to the present invention, it is possible to realize a frequency dividing circuit having a simple configuration in which the frequency dividing ratio can be set arbitrarily and the fluctuation of the interval between the divided clocks can be made within one clock.

[Brief description of the drawings]

FIG. 1 is a block diagram of a frequency dividing circuit according to the present invention.

FIG. 2 is a timing chart of a frequency dividing circuit according to the present invention.

FIG. 3 is a circuit diagram of a conventional binary rate multiplexer.

FIG. 4 is a timing chart of a clock divided by a conventional binary rate multiplexer.

[Explanation of symbols]

 1 frequency divider 2 adder 3 register 4 bus (first input terminal) 5 input line 6 bus 7 bus (second input terminal) 8 output line 9 Y terminal 10 X terminal 11 Z terminal 12 CRY terminal (division) Output terminal) 13 CLK terminal 14 I terminal 15 O terminal

Claims (1)

[Claims] 1. An adder having an M-ary number (M natural number), and a register for latching an addition result of the adder at each rising edge of a reference clock, wherein a first input terminal of the adder has a predetermined input terminal. The value of N (N
A natural number), a latch content of the register is input to a second input terminal, and a divided clock obtained by dividing the reference clock by N / M is output from a carry signal output terminal of the adder. A frequency dividing circuit.