KR900000852Y1 - Control circuit for double extention display - Google Patents

Abstract

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Description

2x magnification display control circuit

1 is a circuit diagram of the present invention.

2 is a waveform diagram of each part of the present invention circuit diagram.

* Explanation of symbols for main parts of the drawings

10: video display unit 2: CRT controller

11: clock resonant circuit 12: counter

FF ₁ , FF ₂ : Flip-flop I ₁ , I ₂ : Inverter

A ₁ -A ₅ : AND gate OR ₁ , OR ₂ : Oagate

The present invention relates to a 2x magnification display control circuit that allows a 2x magnification of a specific line of a screen in a display system of a computer and a terminal.

Conventionally, only the dot clock is divided by 2 times by the 2 times magnification control signal of the CRT controller to display the double width, and this is used as the basic clock of the 2 times magnification display. If the clock frequency is divided into two clocks and the clock clock is used as the basic clock signal, and the frequency is higher than 40 MHz, the video data signal is output to the monitor due to the time delay caused by the division circuit and other gate elements. There was a problem in that the timing did not match during video load (1oad) and shift (shift).

In consideration of the above, the present invention allows the video dot clock and the video load clock to be divided into 2 times each in synchronization with the 2 times magnification output signal of the CRT controller during the 2 times magnification display, regardless of the frequency of the dot clock. In order to provide a circuit that can match timing during video loading and shifting, a video display system comprising a CRT controller, a video RAM, an attribute RAM, a character generator ROM, and an attribute control logic. It is configured to divide video dot clock and video load clock into 2 times each of the CRT controller by dividing them for normal width and 2 times magnification display.

When the present invention as described in detail by the accompanying drawings as follows.

1 is a circuit diagram of the present invention, a microprocessor 1, a CRT controller 2, a video RAM 3, a character generator ROM 5, an attribute RAM 4, an attribute control logic 6, and a shift. In the video display system in which the video display unit 10 is constituted by the registers 7 and 8, the circuit for controlling the normal display and the double magnification display is configured as follows.

First, the dot clock output from the clock oscillation circuit 11 is configured to be applied to the clock input terminal CLK of the frequency division counter 12 and the clock input terminal D of the D flip-flop FF1 for dot clock dividing. It is configured to be applied to the AND gate A5 for use as a video dot clock during normal display, and the output terminal Qc output of the counter 12 is applied to the clock input terminal CK of the CRT controller 2 as a character clock. In addition, the inverter is configured to be applied to the clock input terminal D of the D flip-flop FF2 after passing through the inverter I1 for two divisions of the simultaneous character clock.

In order to divide the output of the output terminal Tc of the counter 12 into two, the output terminal Q _B , Q _C .Q _D of the counter 12 and the flip-flop FF ₂ are provided on the input side of the AND gate A _l . ), the output terminal (Q) output is configured to be applied to each output of the aND gate (a _l) of the configuration is to be applied to the input side of the aND gate (a _2).

In addition, the output terminal (Q) output of the flip-flop (FFl) is applied to the input side of the AND gate (A ₄ ) for use as a video dot clock in the 2 times magnification display, and the 2 times enlarged output terminal (DW) of the CRT controller (2). ) Is applied to the input side of the AND gate A ₂ (A ₄ ) and to the clear terminal CL of the flip-flop FF _I and at the same time through the inverter I ₂ and then to the AND gate A ₃ (A ₅ ). Is applied to the input side.

And the output of the AND gate (A ₂ ) (A ₃ ) is through the oragate (OR,) and then the shifted input terminal (T / S) of the shift register (7) and the load holder input terminal (L) of the register (8) / H) and the output of the AND gate A ₄ (A ₅ ) is applied to the clock input terminal CP of the shift register 7 and the register 8 after passing through the oragate OR ₂ . It is made up.

Thus configured dot clock of the clock banjin circuit 11 in the present design is a flip side of another type of being applied to the input AND gate (A _l) of the AND gate (A ₁₎ after the frequency division is applied to the frequency division counter 12 for therefore be applied in which the clock pulse frequency divider in peulrup (FF ₂₎ to the output side of the aND gate (a _l) is output to the clock signal as in the second degree (a) is to be applied to the input side of the aND gate (a ₂₎ At this time, the output of the output terminal Tc of the counter 12 is applied to the input side of the AND gate A ₃ as shown in FIG. 2B for use as a video load clock in normal display.

That is, the output of the output terminal Tc of the counter 12 is applied to the input side of the AND gate A ₃ for use as a video load clock in normal display as shown in (B) of FIG. 2 and the AND gate A ₁ . On the output side of the counter 12, the output is divided and applied to the input side of the AND gate A ₂ as a video load clock during double magnification display as shown in FIG.

That is, an output such as (A) of FIG. 2 divides the output of (B) of FIG.

The dot clock of the clock resonant circuit 1 is output as shown in (D) of FIG. 2 and applied to the input dot of the AND gate A _{5 as} a video dot clock in normal display and to the flip flop FF ₁ . After 2 minutes, it is applied to the input side of the AND gate A ₄ as the video dot clock in the 2 times magnification display as shown in FIG.

In other words, an output such as (C) of FIG. 2 is divided into two (D) outputs of FIG.

Thus, the video load clock in the 2 times magnification display as shown in (A) of FIG. 2 and the video load clock in the normal display as shown in FIG. 2 (B) and the 2 times the enlarged video dot clock as shown in (C) in FIG. The output of the AND gates A ₂ -A _{5 to} which the video dot clock is applied as shown in (D) of FIG. ₂ is controlled by the output level of the double magnification starter DW of the CRT controller 2. .

That is, when the screen display is a normal display, since the low level status signal is output from the 2x magnification output terminal DW of the CRT controller 2, the flip-flop FFl maintains the cleared relative and the AND gate A _2. (A ₄ ) remains blocked.

The low level output of the 2 times magnified output terminal (DW) of the CRT gon controller 2 is inverted by the inverter I2 and is input to the AND gate A ₃ (A ₅ ) at a high level so that the AND gate A _{2 is applied.} The output of A ₄ becomes low level and the output of the AND gate A ₃ (A ₅ ) is output as in (B) and (D) of FIG.

And the output of the AND gate (A ₃ ) (A ₅ ) is through the oragate (OR _l ) (OR ₂ ) and then to the shift register 7 and the register (8) video load clock as in (B) of FIG. 2. Normal display is achieved by applying the video dot clock as in (D).

However, when the screen display is used as the 2x magnification display, the high level status signal is output to the 2x magnification output terminal (DW) of the CRT controller (2). ₃ ) (A ₅ ) is maintained in the blocking state and the AND gates A2 (A ₄ ) are in the operating state.

Therefore, the video load output during double magnification display is output to the output side of the AND gate A _{2 as} shown in (A) of FIG. 2, and to the output side of the AND gate A ₄ from (C) of FIG. 2. The video dot clock is output during the 2x magnification display, and the output of the end gate A ₂ (A ₄ ) is the post-shift register 7 and the register 8 through the ora gate OR _l (OR 2). ) Is applied to the video load clock and the video dot clock.

In other words, the video load clock as shown in (B) of FIG. 2 and the video dot clock as shown in (D) of FIG. 2 are applied during normal display display, and the video as shown in (A) of FIG. The load clock and the video dot clock as in (C) of FIG. 2 are applied.

Therefore, the video data output from the character generator ROM (5) during normal screen display or 2x magnification display is loaded into the shift register (7) when the video load clock is high level, and at the rising edge of the video dot clock. It is shifted to display a screen of a desired size.

As described above, the present invention is a video display system that requires a 2x magnification display, and the video dot clock and the video load clock generated during normal display and 2x magnification are synchronized in two times in synchronization with the 2x magnification output signal of the controller. This allows the timing of video loading and shifting to be matched regardless of the frequency of the dot clock, which can be widely applied to timing conversion circuits of computers and terminals requiring various displays.

Claims (1)

CRT controller (2) to microprocessor (1). Video RAM (3). Attribute RAM (4). Character generation ROM (5). Attribute control logic (6). Shift register 7. In the video display system to which the display unit 10 composed of the registers 8 is connected, the dot clock of the clock oscillation circuit 11 is applied to the cool clock terminal of the counter 12 and the flip-flop FF ₁ and the AND gate ( A ₅ ) and the output of the output terminal Tc of the counter 12 is applied to the AND gate A ₃ while the output of the output terminal Q _B .Q _C .Q _D is the AND gate A _l ), and the output terminal Q _C of the counter 12 is applied to the clock terminal CK of the CRT controller 2, and at the same time through the inverter I ₁ and the flip-flop FF2. a gate output of the configuration to be applied to the aND gate (a _l) to (a _l) is the aND gate (a ₄₎ is applied to the post configured to be applied to the output of the aND gate (a _l) of the flip-flop (FF ₁₎ CRT The 2x enlarged output terminal (DW) output of the controller (2) is the clear terminal (C) of the AND gate (A ₂ ) (A ₄ ) and the flip-flop (FF _l ). L) and then with applied as soon at the same time the inverter (I ₂₎ to the AND gate (A ₃₎ (A ₅₎ configured to be applied to, and the AND gate _{(A 2) (A 3)} (A 4) the output of the (A ₅₎ A double enlarged display control circuit configured to be applied to the shift register 7 and the register 8 by a video load clock and a video dot clock through an oragate OR ₁ and OR ₂ .