JPS6376617A - Odd number frequency-dividing circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit suitable for forming an LSI by obtaining the OR of the odd number frequency-dividing clock obtained by odd-number- frequency-dividing an input clock and the clock to half-bit-shift the odd number frequency-dividing clock with a D type flip-flop into which a phase-reversal clock is inputted, when the odd number frequency-dividing clock is obtained. CONSTITUTION:The output of an odd number frequency-dividing means and the output of a D type flip-flop 4, to which a phase-reversal clock is inputted in order to half-bit-shift an odd number frequency-dividing means output are constituted to be added to an OR circuit 5. Namely, for an odd number frequency-dividing clock from the odd number frequency-dividing means 1 and the clock to half-bit-shift the odd number frequency-dividing clock with a phase- reversal clock by the D type flip-flop 4, the OR is obtained by an OR means 5 and the odd number frequency-dividing clock of a duty factor 50% is obtained. Thus, by miniaturizing and decreasing an adjusting place, a circuit constitution suitable to forming an LSI is obtained.

Description

[Detailed Description of the Invention] [Summary] In an odd frequency dividing circuit, when obtaining an odd frequency divided clock with a duty factor of approximately 50χ, an odd frequency divided clock obtained by dividing an input clock by an odd number, By using a D-type flip-flop to which an anti-phase clock is input, the logical sum is obtained by shifting this odd-numbered frequency-divided clock by half a bit.

It is designed to be suitable for LSI implementation.

[Industrial application field]

The present invention relates to an improvement in an odd frequency divider circuit.

Generally, the duty factor of the clock supplied to a digital circuit is often specified as 1, for example, 5o±1oχ, but in the case of a divide-by-3 circuit, if the frequency remains divided, the duty factor will be 1/3.5. In the case of Zhou, it is 215,
Since it is difficult to satisfy this regulation, a circuit is added to set the duty factor to 50χ.

On the other hand, in recent years, in response to the miniaturization of devices, circuits have been made into LSIs, so it is necessary that this odd frequency divider circuit also have a circuit configuration suitable for LSIs.

[Conventional technology]

FIG. 4 is a block diagram of a conventional example, and FIG. 5 shows output waveforms of main parts of FIG. 4. Numbers on the left side of FIG. 5 indicate waveforms of portions with the same numbers in FIG. 4. The operation of FIG. 4 will be described below with reference to FIG. 5 in the case where the input clock frequency is divided by three.

First, when the power is turned on (POWO
D-type flip-flop (hereinafter referred to as D-
Assuming that the terminal Q of 1) 12 (abbreviated as FF) is set to 1, H is added to the terminal of D-FF 1) as shown in Figure 5-■, and this 1) becomes 1. The input terminal Q changes to H at the rising edge of the clock shown in Figure 5-○, and returns to L at the rising edge of the next clock (see the first half of Figure 5-2).

Therefore, as shown in the first half of Figure 5-■, the terminal port of D-FF 12 changes from L to H with a delay of 1 bit from D-FF 1), and then returns to L again. The terminal returns to the initial state H again at the point shown in Figure 5-■ and returns to D-P.
FII and 12 repeat the above operation as indicated by the dotted arrows.

Then, the output of the terminal 0 of the D-FF 12 (a 3-frequency divided clock with a duty factor of 173) is delayed by half a bit by the delay line 2, for example, and then output to the output terminal 0 of the D-FF 12 (hereinafter abbreviated as R3-FF). ) is applied to terminal R of 3 (see Figure 5, ■).

Since the output of the terminal Q of D-FF 1) is applied to the terminal S of this R5-FF, it is set by the output of D-FF 1) and reset by the output of delay line 2, as shown in Figure 5-○. Similarly, a divided-by-3 clock with a duty factor of 50χ is obtained.

[Problem that the invention seeks to solve]

As explained above, since a delay line or multi-stage connected gates are used as the half-bit shift part to set the duty factor to 50χ, a large space is required, or the amount of delay may vary due to deviations in the characteristics of the elements. may be outside the permissible range.

Furthermore, the half-bit shift part must be readjusted to keep the duty factor constant when the clock frequency is changed.

That is, there is a problem in that the circuit structure must be made suitable for LSI implementation by reducing the size and reducing the number of adjustment parts.

[Means for solving problems]

FIG. 1 shows a diagram of the principle of the present invention. The output of the odd number frequency dividing means 1 and the output of a D type flip-flop 4 to which an antiphase clock is input in order to shift the output of the odd number frequency dividing means by half a bit are added to an OR circuit 5.

[Effect]

In the present invention, the odd number frequency divided clock from the odd number frequency dividing means 1 and the half bit shift of this odd number frequency divided clock using a D type flip-flop 4 using an anti-phase clock are logically summed by the OR means 5. Take the duty factor 50χ
The circuit configuration is made suitable for LSI by obtaining an odd-number frequency-divided clock to reduce the size and adjustment parts.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 shows output waveforms of main parts of FIG. Note that the same reference numerals indicate the same objects throughout the figures, and the numbers on the left side of FIG. 3 indicate the waveforms of the numbers in FIG. 2. Further, in the present invention, the OR circuit 5' is used as a logical sum means.

The operation of FIG. 2 will be described below with reference to FIG. 3 using frequency division by 3 as an example.

First, D-FF 1). The operation of the odd frequency dividing means 1 consisting of the NOR circuit 12 and the NOR circuit 13 is as described above and as shown in FIGS.

As shown by the dotted line arrow (2), the duty factor 1/3 divided-by-3 clock output from terminal Q of D-FF 1) is shifted by 1 bit and transferred from terminal 0 of D-Pri 12 to D
-I'F is added to the terminal of 4.

Since this D-FF 4 is supplied with an anti-phase clock whose phase is inverted with respect to the clock shown in Figure 3-0, the output of D-FF 12 is shifted by half a bit and output from the terminal. (See Figure 3 - ■, ■).

Then, the outputs of D-FF 12 and D-FF 4 are logically summed with an OR circuit of 5 degrees, and a 3-frequency divided clock with a duty factor of approximately 50X is obtained as shown in Figure 3-■. .

In addition, although the above explanation was about frequency division by 3, frequency division by 5, frequency division by 7
In the case of frequency division, an output with a duty factor of 275°377 is obtained, so by half-bit shifting I using the half-bit shift means 4, the output is 55° as in the case of frequency division by 3.
Around the duty factor of 0χ, [:Jtsuk] is obtained.

That is, in order to shift the focus by half, an anti-phase clock and one D-FF are used instead of a delay line or gates connected in multiple stages, so the space is small and the deviation in characteristics is small. Furthermore, since there is no need for adjustment even if the clock frequency is changed, this odd number frequency dividing circuit is suitable for LSI implementation.

〔Effect of the invention〕

As explained in detail above, the present invention has the advantage that an odd number frequency divider circuit suitable for LSI can be obtained.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention. FIG. 2 is a block diagram of an embodiment of the present invention. 1 is an odd number dividing means; 4 is D type-flip-flop, 5 indicates a logical sum means. eo ■ @■ @ O

Claims (1)

[Claims of Claims] A D type in which an odd frequency dividing means (1) that divides an input clock by an odd number, and an output of the odd frequency dividing means and an anti-phase clock whose phase is inverted with respect to the input clock are input. An odd number frequency dividing circuit comprising: - a flip-flop (4); and an OR means (5) for ORing the output of the odd number frequency dividing circuit and the output of the D type flip-flop.