JPS6388905A - Fm signal demodulator - Google Patents

Abstract

PURPOSE:To decrease the processing word length of an inverse tangent computing element by limiting the output word length of a digital filter in response to the output of a level detection circuit. CONSTITUTION:A frequency modulation signal inputted to an input terminal 1 is inputted to digital filters 2, 3. The phase characteristic of the filters 2, 3 is deviated with each other by 90 deg.. Outputs Ei, Er of the filters 2, 3 are processed by absolute value circuits 5, 6 and a logic adder circuit 7 and a detection circuit 8 detects from which bit order a bit goes to '1' starting from the most significant bit and a signal is generated to shift shoft registers 12, 13. The output of the registers 11, 12 is rounded off by the low-order bit by high- order bot extraction circuits 14, 15 and the output of the circuits 14, 15 is subjected to address designation of an inverse tangent arithmetic circuit 16.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an FM signal demodulation device that demodulates a frequency modulated signal by digital signal processing.

2. Description of the Related Art In recent years, there has been a demand for demodulating frequency modulated signals by digital signal processing, and demodulators having a circuit for calculating inverse trigonometric functions have been used. The above-mentioned conventional FM signal demodulation device will be described below with reference to the drawings.

FIG. 3 is a block diagram of a conventional FM demodulator. Third
In the figure, 20 is an input terminal, 21 and 22 are digital filters, 23 is a divider, 24 is an arctangent calculator for calculating an arctangent, 26 is a differentiator, and 26 is an output terminal.

The operation of demodulating a frequency modulated signal using the FM signal demodulation device configured as described above will be described below.

A sampled signal is input to the input terminal 2o and applied to digital filters 21 and 22.

The output Er of the digital filter 21 and the output E of the digital filter 22 are the E, /E input to the divider 23.
r is calculated. The output of the divider 23 is added to an arctangent calculator 24 that calculates the arctangent,
E r) is output. If the amplitude characteristics of the digital filters 21 and 22 are the same and the phase equality is shifted by 90° within the band where the FM signal exists, li:i=A sinθ,
It can be expressed as E r=Acosθ, and arctangent calculator 24
The output becomes the phase θ of the FM signal. Arctangent calculator 24
The output of is applied to a differentiator 25, and the rate of change in phase is obtained at an output terminal 26 of the differentiator 25. In other words, at the output terminal 26, a sample value of the phase fluctuation rate of the frequency modulation signal, that is, a sample value of the demodulated signal is obtained.

Problems to be Solved by the Invention However, in order to obtain a good demodulated output even when the level of the frequency modulated signal increases or decreases from the reference level in the above-mentioned device, it is necessary to use a demodulator. The internal processing word length must be increased. Therefore, when the input/output word length of the divider or arctangent calculator is large,
The circuit scale of the demodulator becomes too large.

In view of the above-mentioned problems, the present invention provides an FM signal demodulation device which has a small circuit scale and which can provide a good demodulated output even when there are fluctuations in the level of the FM signal.

Means for Solving the Problems In order to solve the above problems, the FM signal demodulation device of the present invention has a frequency modulation signal that is inputted with a sampled frequency modulation signal and has equal amplitude characteristics in the band where the frequency modulation signal exists. Two digital filters whose phase characteristics are shifted by 90',
a level detection circuit that detects the signal level from the output of two digital filters, a word length limiting circuit that limits the word length of the output of the digital filter according to the output of the level detection circuit, and an arctangent value of the output ratio of the word length limiting circuit. It is equipped with an arctangent calculation circuit that outputs an output, and a differentiator that differentiates the output of the arctangent calculation circuit.

Operation The present invention reduces the processing word length of the arctangent calculator by limiting the output word length of the digital filter according to the output of the level detection circuit with the above-described configuration.

Moreover, since word length limitation is performed according to the signal level of the FM signal, a good demodulated signal can be obtained even if the level of the FM signal increases or decreases.

Embodiment Hereinafter, an FM signal demodulator according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of an FM signal demodulator according to an embodiment of the present invention. In Figure 1, 1 is an input terminal, 2 and 3 are digital filters, 4 is a level detection circuit, 5 and 6 are absolute value circuits, 7 is a logical addition circuit for each pit, and 8 detects the highest pit that is not zero. Detection circuit, 9 is a shift signal generation circuit, 10
and 11 are word length limiting circuits, 12 and 13 are shift registers,
14 and 16 are upper pit extraction circuits, 16 is an arctangent calculation circuit 17 constructed using a ROM, etc., is a differentiator, and 18 is an output terminal.

The FM signal demodulation device configured as described above will be explained below using FIG. 1 and FIG. 2 which shows the operating states of the level detection circuit and word length limiting circuit in FIG. 1 by taking a specific case as an example. do. Note that the output word length of the digital filter and the output word length of the word length limiting circuit are arbitrary, but for ease of explanation here, it is assumed that the output word length of the digital filter is 8 bits and the output word length of the word length limiting circuit is 8 bits. An example in which the data is 4 bits will be explained.

In FIG. 1, a frequency modulated signal input to input terminal 1 is transmitted to digital filter 2 and digital filter 3.
is input. The digital filters 2 and 3 are made to have equal amplitude characteristics within the band where the frequency modulation signal exists, and have phase characteristics shifted by 90'. At this time, the output of the digital filter 2 can be expressed as E i=As1nθ, and the output of the digital filter 3 can be expressed as E=Acosθ. Here, assume that Ei and Er are expressed in binary numbers as shown in FIG. Ei and E are respectively processed by the absolute value circuit to become IEil and IE,1. This IEil
Let F be the result of Er1 processed by the logic adder T for each pit from the most significant bit to the least significant bit. Furthermore, the detection circuit 8 detects which bit counting from the uppermost bit of F becomes 1 for the first time. In the example in Figure 2, F
Since the fourth bit from the most significant pit becomes 1 for the first time, the output of the detection circuit 8 becomes 1 only at the 4th bit.

When the shift signal generating circuit 9 receives an input in which only the nth bit is 1, the shift signal generating circuit 9 outputs n to the shift registers 2 and 13.
Generate a signal to shift by -2 bits. Second
In the example shown, the shift register is given a signal to shift by 2 bits, so the output of shift register 2 is 4EL, and the output of shift register 3 is 4Er.
become. Furthermore, the lower pits of the outputs of the shift registers 2 and 13 are truncated by upper bit extraction circuits 16 and 14, respectively.

In the example in Figure 2, the lower 4 bits are used to limit the word length to 4 bits.
Bits are truncated. Upper bit extraction circuit 15
The output R of the upper bit extraction circuit 14 and the output R of the upper bit extraction circuit 14 serve as the address specification of the arctangent calculation circuit 16. Arctangent calculation circuit 1
6 stores “tan” (I/R).I:4
Since As1nθ, R=4 Acosθ, the output of the arctangent calculation circuit 16 becomes the phase θ of the FM modulation signal.

This θ is differentiated by a differentiator 17 to obtain a demodulated signal of the FM modulation signal.

In this embodiment, the word length setting image is explained in which the output of the digital filter is 8 bits and the output after word length limitation is 4 bits, but this is not necessarily the case.

Furthermore, the configurations of the level detection circuit and word length limiting circuit do not necessarily have to be as in this embodiment.

Further, the arctangent calculation circuit may be a calculation circuit having similar calculation capability.

Effects of the Invention As described above, the FM signal demodulation device of the present invention has two signals having equal amplitude characteristics and a phase difference of 90° in the band where the sampled frequency modulation signal is input and where the frequency modulation signal exists. a digital filter; a level detection circuit that detects signal levels from the outputs of the two digital filters; a word length limiting circuit that limits the word length of the output of the digital filter according to the output of the level detection circuit; By providing an arctangent calculation circuit that outputs the arctangent value of the ratio and a differentiator for the output of the arctangent calculation circuit, it is possible to obtain a good demodulated signal even if the input signal level fluctuates. Furthermore, since the word length is limited before calculating the arctangent, the arctangent calculating section, which was conventionally very large, has become smaller, and the circuit scale of the entire demodulator has been reduced.

The FM signal demodulator of the present invention can perform level detection without any time delay in response to input level fluctuations, so it can always follow even if the input signal level changes suddenly.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of an FM signal demodulator according to an embodiment of the present invention, Fig. 2 is a schematic block diagram of main parts for explaining the operation of each part, and Fig. 3 is a conventional FM signal demodulator. FIG. 1... Input terminal, 2, 3... Digital filter, 4... Level detection circuit, 5, 6...
...Absolute value circuit, 7...Logic addition circuit,
8...Detection circuit, 9...Shift signal generation circuit, 10, 11...Word length limiting circuit, 12.
13...Shift register, 14.15...
... Upper bit extraction circuit, 16 ... Arctangent calculation circuit, 17 ... Differentiator, 18 ... Output terminal.

Claims (1)

[Claims] a first digital filter into which the sampled frequency modulation signal is input; and a first digital filter into which the frequency modulation signal is input and which has an amplitude characteristic equal to that of the first digital filter and a phase characteristic in a band where the frequency modulation signal exists. 90
a second digital filter that is shifted by a degree, a level detection circuit to which the output of the first digital filter and the output of the second digital filter are input;
a first word length limiting circuit to which the output of the digital filter is input, and which is controlled by the output of the level detection circuit to extract and output a part of the word length of the output value of the first digital filter; The output of the second digital filter is inputted and controlled by the output of the level detection circuit.
a second word length limiting circuit that extracts and outputs a part of the word length of the output value of the digital filter; the output of the first word length limiting circuit is used as a first input; an arctangent calculation circuit that uses the output of the limiting circuit as a second input and outputs an arctangent value of the ratio of the first input and the second input;
An FM signal demodulator comprising: a pulverizer into which the output of the arctangent calculation circuit is input.