JPS62216505A - Digital fm demodulation circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale by applying logarithmic conversion to digital FM signals having a phase difference of 90 deg., applying the subtraction processing to both and then applying exponential conversion. CONSTITUTION:Absolute values ¦sintheta¦, ¦costheta¦ of two digital FM signals sintheta, costheta having a different phase of 90 deg. are given respectively to ROMs 21, 22. The ROM 21, 22 have respectively a loge table, and an input data is used as an address data to apply logarithmic conversion. Logarithmic conversion outputs loge¦sintheta¦, loge¦costheta¦ of the ROMs 21, 22 are subjected to subtraction processing by a subtracter circuit 23. The ROM 24 has a table of exponent-tan<-1> table, the input data is used as the address table and the result of subtraction is subject to exponent-tan<-1> conversion. The phase data theta (=tan<-1>e<x>) is given to a phase expansion circuit 16. Thus, the capacity of the ROMs in use is reduced conventionally.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a digital FM demodulation circuit.

(Prior Art) An example of a conventionally considered digital FM demodulation circuit is the one shown in FIG.

In the illustrated circuit, the digital FM signal Amθ is first given to the phase shift circuit 1. This phase shift circuit 11
outputs one of the input signals SK as is, and one with a phase shift of 90°.

These two output signals, blood θ and AQIIθ, are converted to absolute values IA and θ1, 1Aco by the absolute value circuit 12.13, respectively.
sθ1 is taken. These two absolute values IAmθ1. I
AQllθ1 is divided by a division circuit 14.

This division value lt-θ1 is the RO where the m-1 table is stored.
This is the address data of M15. As a result, 几0M
Phase data θ within the range of 0 to 15 is output from 15. This data θ is given to the phase expansion circuit 16, and the output 1 of the phase shift circuit 1 is As1nθ, AQIIθ.
is converted into phase data θ' in the range of -π to π. By inputting this phase data θ' to the differentiating circuit 17, it is possible to obtain similar signal data.

dt However, in the case of the above configuration, the output accuracy of the 0M15 is 11 bits with 8 bits and 2's complement display input.

If you try to use the same address as 0M15, 21 pins will be required. As a result, the capacity of the ROM 15 becomes as large as 2×11=23 megapits.

Furthermore, the division circuit 14 also requires a 7-pin subtraction circuit corresponding to the number of output digits, which results in a large scale.

(Problems to be Solved by the Invention) As described above, the conventional digital FM demodulation circuit has the problem of increasing the circuit scale.

Therefore, an object of the present invention is to provide a digital FM demodulation circuit that can reduce the circuit scale.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a first . A digital FM demodulation circuit configured to include means for logarithmically converting the second digital FM signal, means for subtracting the two logarithmically converted outputs, and means for exponent-1-1 converting the subtraction process output. It is.

(Operation) According to the above configuration, the reduction fI of logarithms having the same base
Since LFi is equal to the logarithm whose argument is the division result of its argument, it is possible to divide two digital FM without using a division circuit.
It becomes possible to divide the signal.

Furthermore, since the exponent-1-1 conversion is more linear than the tu-1 conversion, if this conversion is implemented in a ROM, the capacity of the ROM can be reduced.

From the above, in the above configuration, the circuit scale can be reduced.

(Embodiment) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention.

In Fig. 1, two digital FM signals θ having a phase difference of 90' from each other, (2) Absolute value of θ 1 θ 1° 1 cm
The process up to the point where 01 is taken is the same as in FIG. 2 above.

These two absolute values l*010■01 are RO
M21.22 is given. Each of these ROMs 21 and 22 has a log e table, and logarithmically transforms the input data as address data.

Logarithmic conversion output of 几0M21.22 log e 1 sin
θ1.

1 ogel■θI is subjected to subtraction processing in the subtraction circuit 23.

The result of this subtraction is

X=logeldnθl−1ogelccgθ1=
It is expressed as log e ltmθ1. The ROM 24 has an index-tu-' table, which uses input data as address data and converts it into an index-tu-' table.
tu-1 conversion. As a result, from 几0M24, 0
Phase data θ in the range of ~T is obtained. This phase data θ is expressed as follows: θ=-〇This phase data θ is given to the phase expansion circuit 16,
The subsequent operations are the same as those shown in FIG. 2 above.

According to this embodiment detailed above, the signal ratio θ.

The division of 40 can be done using the subtraction circuit 2 without using the division circuit.
This can be done using 3. The circuit scale ratio between the division circuit and the subtraction circuit is approximately equal to the number of digits of the division quotient. Therefore, according to this embodiment in which the division circuit can be replaced with the subtraction circuit 23, the circuit scale can be significantly reduced compared to the conventional one.

Also, the index-1 table is more linear than the txa-' table.

Therefore, the capacity of ROM 24 is reduced to ROM 15 in FIG.
The capacity can be significantly reduced.

For example, if we assume that the output accuracy of 0M24 is equivalent to 11 pits with an 8-bit two's complement display input, then RO
The required number of pits for M24 is 2048 x 11 pits, which is much smaller than the required number of bits for M15, which is 23 megabytes. However, in the case of this male side, I for logarithmic conversion
'LOM 22, 22 are required, but the number of bits for each is at most 128 x 10 bits. Therefore, even if the required number of bits of each ROM 21, 22, and 24 is combined, it is about 25 kilobits, which is much smaller than the required number of bits of the fLOM 15, which is 23 mef bits.

In this way, in this embodiment, the capacity of the ROM used can be made much smaller than in the prior art, and from this point of view as well, the circuit scale can be reduced.

Although one embodiment of this invention has been described in detail above, this invention is not limited to this embodiment, and it goes without saying that various other modifications can be made without departing from the gist of the invention. It is.

[Effects of the Invention] According to the invention described above, it is possible to provide a digital FM demodulation circuit that can reduce the circuit scale.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a circuit diagram showing the configuration of a conventional digital FM demodulation circuit. 11... Phase shift circuit, 12.13... Absolute value circuit, 16... Phase expansion circuit, 12... Differential circuit, 2
1.22.24...ROM.

Claims (1)

[Claims] Phase shifting means for phase shifting a digital FM signal and outputting first and second digital FM signals having a phase difference of 90 degrees; Logarithmic conversion means for converting, subtraction means for subtracting logarithm conversion outputs of the first and second digital FM signals, and exponent -tan^- for converting the output signal of the subtraction means by -tan^-^1. A digital FM demodulation circuit equipped with ^1 conversion means.