JPH0322624A - A/d converter - Google Patents

Abstract

PURPOSE:To calculate a low level signal and a high level signal at the time of processing the signal with a digital code having similar information quantity by shifting an output data of a 1st down-sampling circuit according to the shift extent, and inputting the result to a 2nd down-sampling circuit. CONSTITUTION:An output signal of an A/D converter 1 is inputted to a 1st down-sampling circuit 2 to output an N-bit natural binary code through a loopback noise suppression filter. Moreover, an amplitude detection circuit 3 receives an output data of the 1st down-sampling circuit 2 to output the amplitude. A shift quantity decision circuit 4 receives amplification factor to decide the shift. A shift circuit 5 receives an output data of the 1st down-sampling circuit 2 to apply left logic shift calculation according to the output signal of the shift quantity decision circuit 4 and a high-order M-bit is inputted to the 2nd down-sampling circuit 6. Then 16-bit effective value is inputted to the 2nd down-sampling circuit 6 even as to a low level signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an A/D conversion device, and particularly to an A/D conversion device that is widely used in digital signal processing and converts an analog signal into a digital signal. [Prior Art] In recent years, with the development of microprocessors, high-speed and high-precision signal processors have appeared in the signal processing field. For this reason, A/D converters that convert analog signals into digital signals are also required to perform highly accurate processing.
Recently, A/D conversion converts an analog signal into a digital signal at a high sampling frequency using an oversampling method using a predictor and a noise shaper, and then converts it to the desired sampling rate using a digital filter and downsampling. Many devices are used. This reduces the size of the analog components and performs A/D conversion using digital signal processing to achieve high S/N.
It is intended to obtain properties. FIG. 6 is a block diagram of an A/D conversion device showing an example of such a conventional device. As shown in Fig. 6, this device combines the conventional primary predictor and the
represents a signal processing system of an oversampling A/D converter consisting of a noise shaper, i.e.
The A/D converter 1 has a frequency f. The input analog signal is converted to a digital signal by sampling and output. In addition, the first downsampling circuit 2 downsamples the output data of the A/D converter 1 from the sampling frequency f, to f2 (fs > fz), has the function of an aliasing noise suppression filter, and has the function of an aliasing noise suppression filter. Assume that is 22 bits. Further, the second downsampling circuit 3 further downsamples the output data of the first downsampling circuit 2 from the sampling frequency f2 to f, (fz > fs), and also prevents aliasing noise at this time and limits the band. Assume that it is a signal processor that has a 16-bit length external data interface and a 16-bit length internal calculation capability. When performing signal processing using such a system, the digital code output from the primary downsampling circuit 2 is 22
The range of levels that can be expressed using a natural binary code of bits is from OdB to approximately -132dB. On the other hand, since the secondary downsampling circuit 3 is a signal processor with a 16-bit external interface and a 16-bit internal calculation capability, Input 16 bits. Therefore, even if the output data of the first downsampling circuit 2 is -100dB, the input data of the second downsampling circuit 3 is 16 bits, so all input data of -97dB or less is "O". Become. That is, when the output data of the first downsampling circuit 2 is between -97dB and -132dB, the second
All inputs to the next downsampling circuit 3 become "O". Therefore, the calculation error between the first downsampling circuit 2 and the second downsampling circuit 3 increases. Figure 7 shows OdB and -48dB in Figure 6.
The total number of bits is 22 bits《
This is a correspondence diagram showing the result of conversion into a natural binary code using an A/D converter (8 bits for the integer part and 14 bits for the decimal part) and a primary downsampling circuit. As shown in FIG. 7, in the above-mentioned signal processing system, if the input data is data close to OdB of the high level signal, the upper 16 bits of the 22 bits of output data from the primary downsampling circuit 2 The second downsampling circuit 3 assumes that all bits are valid data.
is input into . On the other hand, if the input data is data close to -90 dB of the low level signal, as shown in FIG. The data becomes invalid, and only the lower several bits of the 16 bits of input data to the secondary downsampling circuit 3 become valid, and each time the input data becomes a low level, the input data to the secondary downsampling circuit 3 becomes invalid. The number of bits will be a few bits or zero pits, and most of the information will be lost. [Problems to be Solved by the Invention] When the conventional differential A/D converter described above is used, the first
Although the output data of the secondary downsampling circuit is N bits, the input data of the secondary downsampling circuit is M bits (N>M>), so only the upper M bits of the N bits are valid data. As a result, the information from the upper (M+1)th bit to the N bit of the output data of the first downsampling circuit becomes invalid.
It has the disadvantage of increasing calculation errors when performing low-level signal processing. An object of the present invention is to provide an A/D conversion device that can process low-level signals in the same way as high-level signals and can reduce calculation errors. [Means for Solving the Problems] An A/D conversion device of the present invention includes a differential A/D converter that samples at a frequency ft, and output data of the A/D converter at a sampling frequency f. from f2 (f+ >
a first downsampling circuit that downsamples the frequency fz) and has the function of an aliasing noise suppression filter; and an amplitude detection circuit that inputs the output data of the first downsampling circuit at each frequency f2 and detects the amplitude of the data. a shift determination circuit that determines a shift amount as a result of the amplitude detection circuit during a certain predetermined period, outputs this shift amount, searches for the minimum shift amount, and outputs the minimum shift amount after the predetermined period; , a shift circuit that shifts the output data of the first downsampling circuit based on the output of the shift amount determining circuit, and a frequency fz (fz >
ft), and a second downsampling circuit that downsamples again at ft) and outputs a digital signal. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an A/D conversion device showing an embodiment of the present invention. As shown in FIG. 1, in this embodiment, an A/D converter 1 converts an analog signal into a digital signal by sampling at a frequency f1 using a predictor and a noise shaper, and outputs a natural binary code. and output data of the A/D converter 1 at sampling frequency f. from f2 (ft >f2>
a first downsampling circuit 2 that downsamples the signal and has the function of an aliasing noise suppression filter and outputs N bits; An amplitude detection circuit 3 that outputs amplitude degree, and an amplitude detection circuit 3
The output of is input for each frequency f2, and in a certain predetermined period T, the shift amount is determined from this input value and the shift amount is output, and the minimum shift amount is searched, and after a certain predetermined period T, the minimum shift amount is determined. A shift amount determination circuit 4 outputs the amount, a shift circuit 5 performs a left logical shift operation on the output data of the primary downsampling circuit 2 based on the output of the shift amount determination circuit 4, and the output data of the shift circuit 5 is sampled. It has the function of further downsampling the frequency from f2 to fs (f2>f3), preventing aliasing noise at this time and limiting the band, as well as an M-bit (N>M) length external data interface and M-bit length internal processing capacity. and a second downsampling circuit 6. That is, the upper M bits of the output data of the shift circuit 5 are input to the second downsampling circuit 6. Next, in the system that performs the signal processing described above, oversampling A/D conversion using a predictor and a noise shaper when high-level input analog signals and low-level input analog signals are randomly input. The operation of the device will be explained. First, in the oversampling type A/D converter using a predictor and a noise shaper in this embodiment, when an analog signal is input to the A/D converter 1, the frequency f. , and convert the analog signal into a digital signal using a predictor and a noise shaper. This A/
The output signal of the D converter 1 is input to the first downsampling circuit 2, and the sampling frequency f1 to fz (f
t > f2), and passes through an aliasing noise suppression filter to output an N-bit natural binary code. Further, the amplitude detection circuit 3 receives the output data of the first downsampling circuit 2, detects the amplitude of this input data, and outputs the degree of amplitude. The shift amount determination circuit 4 inputs the amplitude degree output of the amplitude detection circuit 3 and determines the shift amount from this value. At this time, in a certain predetermined period T, the determined shift amount is outputted, and at the same time, the minimum shift value in the certain predetermined period T is searched. Also, after a certain predetermined period T, this minimum shift amount is output. That is, in a certain predetermined period T, the shift amount for the maximum amplitude data of the output data of the first downsampling circuit 2 is searched. Further, the shift circuit 5 inputs the output data of the first downsampling circuit 2 and performs a left logical shift operation according to the output signal of the shift amount determining circuit 4. Figure 2 is a diagram showing the data structure for shifter operation inside the shift circuit in Figure 1. As shown in FIG. 2, this shifter operation data represents the relationship between the M-bit fetched data and the shift amount in the N-bit data, that is, a left logical shift. The upper M bits after the left logical shift operation are input to the second downsampling circuit 6. The second downsampling circuit 6 further converts the output data of the shift circuit 5 from the sampling frequency f2 to fs (f2>fs)
The signal is down-sampled to prevent aliasing noise and band-limited to output an M-bit digital signal. For example, an A/D converter 1 converts an input analog signal into a digital signal using a predictor and a noise shaper, and a natural 2
The first downsampling circuit 2 which outputs a 22-bit hex code and the shift amount determination circuit 4 determine the shift amount from the output value of the amplitude degree of the amplitude detection circuit 3 according to a set value. Here, it is assumed that the second downsampling circuit 6 uses a signal processor having a 16-bit length external interface and 16-bit length internal processing capacity. The operation of the oversampling A/D converter using the predictor and noise shaper when an analog signal with a level of -90 dB is input will be described below. Figure 3 is a correspondence diagram of the level determined by the shift amount determining circuit in Figure 1 and the shift amount, and Figure 4 is a diagram showing the correspondence between the level and shift amount determined by the shift amount determination circuit in Figure 1.
This is a correspondence diagram between an analog signal at a level close to B and -48 dB and a 16-bit natural binary code input to the second downsampling circuit. As shown in Figures 3 and 4, the level is -90dB.
In this case, the amplitude detection circuit 3 outputs a value of -90 dB as a detection result, and the shift amount determining circuit 4 outputs a signal corresponding to a shift amount of 14 bits, so the operation is as follows.6 ■ Input The 22 bits output from the primary downsampling circuit 2 at a level of -90 dB are as follows (the underlined part is the upper 16 bits).oooooooooooooo
tooootoo ■ According to Figure 3, the input level is -90
Since it is a dB signal, the shift amount determination circuit 4 outputs a shift amount of "14". ■In the shift circuit, the output value of the shift amount determining circuit 4 is “1”.
4'', the output value of the primary downsampling circuit 2 is logically shifted to the left by 14 bits. 11 1 recommendation 000000000000 ■ After performing the left logical shift in the shift circuit 5, the upper 16 bits are shifted to the left by 14 bits. It is input to the sampling circuit 6. In this way, the shift amount determining circuit 4 and the shift circuit 5 are operated, and the fixed shift amount of the shift amount determining circuit 4 is determined in a certain predetermined period T by the method described above, and the A/D If the output of the converter 1 and the primary downsampling circuit 2 is a 22-bit natural binary code, 16 bits worth of valid values are input to the secondary downsampling circuit 6 even for low-level signals. Next, regarding the second embodiment of the present invention, FIGS.
This will be explained with reference to the figure. The difference in this embodiment from the block configuration of the first embodiment described above is that the A/D converter 1 and the shift amount determining circuit 4
and the operation of shift circuit 5 are different. That is, the A/D converter 1 in FIG. Primary downsampling circuit 2
The point is to perform an arithmetic shift operation on the output data of . In this embodiment, the shift amount determination circuit 4 determines that when the two's complement value, which is the output data of the first downsampling circuit 2, is a positive number, the MSB is "O", so the MSB is "O".
Bits are detected sequentially starting from B, and the number of pits up to the bit before the first bit where ゜゜1゜' is detected is output as the shift amount. Conversely, if the two's complement value that is the output data of the primary downsampling circuit 2 is a negative number, the MSB is "1", so "0" is detected only after sequentially detecting bits starting from the MSB. The number of bits up to one bit before the input bit is output as a shift amount. Fig. 5 shows data for shifter operation inside a shift circuit in an A/D converter for explaining the second embodiment of the present invention. 5 is a configuration diagram. As shown in FIG. 5, the shift circuit 5 shifts (M-1) bits of data based on the determined shift amount. In this way, in this embodiment, the A/D conversion Even when the digital signal output from the circuit 1 is a two's complement code, the shift circuit 5 performs an arithmetic shift operation as shown in FIG. can be input to the second downsampling circuit 6. [Effects of the Invention] As explained above, the A/D converter of the present invention performs the first downsampling according to the shift amount. Shifting the output data of the circuit and inputting this data to the second downsampling circuit, i.e. sampling frequency f2
By further downsampling from f3 (fi > fs >), in digital signal processing, calculations can be performed on low-level signals and high-level signals using digital codes that have the same amount of information, so they are not digitized. This has the effect of not only guaranteeing the effective number of bits of low-level signals, but also reducing calculation errors during digital signal processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an A/D conversion device showing an embodiment of the present invention, FIG. 2 is a data configuration diagram for shifter operation inside the shift circuit in FIG. 1, and FIG. 3 is a shift amount in FIG. 1. Correspondence diagram between the level determined by the determination circuit and the shift amount, 4th
The figure is a correspondence diagram between the analog signal at a level close to OdB and -48 dB in Figure 1 and the 16-bit natural binary code input to the secondary downsampling circuit, and Figure 5 explains another embodiment of the present invention. Shifter operation data configuration diagram inside a shift circuit in an A/D converter for
The figure is a block diagram of an A/D converter showing an example of a conventional A/D conversion device. It is a correspondence diagram showing the result of conversion into a natural binary code using a downsampling circuit. 1...A/
D converter, 2...first downsampling circuit, 3
... Amplitude detection circuit, 4... Shift amount determination circuit, 5.
...Shift circuit, 6...Second downsampling circuit.

Claims (1)

[Claims] a differential A/D converter that samples at a frequency f_1, and a first one that down-samples the output data of the A/D converter from the sampling frequency f_1 to f_2 (f_1>f_2) and has the function of an aliasing noise suppression filter. a downsampling circuit; an amplitude detection circuit that receives the output data of the first downsampling circuit at every frequency f_2 and detects the amplitude of the data; and determines a shift amount from the results of the amplitude detection circuit for a certain predetermined period. a shift determination circuit that outputs the shift amount, searches for the minimum shift amount, and outputs the minimum shift amount after the predetermined period; and the first downsampling circuit based on the output of the shift amount determination circuit. and a second downsampling circuit that downsamples the valid value from the shift circuit again at a frequency f_3 (f_2>f_3) and outputs a digital signal. A/D conversion device.