RU95119581A - VOCODERNY INTEGRAL DIAGRAM OF APPLIED ORIENTATION - Google Patents

Claims (12)

1. Vocoder, characterized in that it contains a digital signal processing processor (DSP), designed to perform recursive calculation of convolution and to output the result of this recursive convolution; and a minimizing processor for receiving the obtained result of the recursive convolution and for performing a minimization search in accordance with the result of said recursive convolution.  2. The device according to p. 1, characterized in that the said DSPC is designed to perform the above recursive convolution on the first sequence and the second sequence and contains computing means for performing the above recursive convolution; first random access memory for storing and issuing said first sequence; a second random access memory for storing and issuing said second sequence; and a third random access memory for storing and outputting additional serial data.  3. The device according to claim 1, characterized in that it comprises means for performing block rationing of the data sequence.  4. A vocoder, characterized in that it contains a DSP having an input for receiving digitized audio data and an output; and a minimizing processor having an input coupled to said PCOS output and an output.  5. The device according to claim 4, characterized in that it further comprises a digitized audio data interface having an input for receiving the first audio data and an output, said DSPC input being connected to said output of the digitized audio data interface.  6. The device according to p. 5, characterized in that it further comprises a microprocessor interface having an input for receiving microprocessor data and an output, said digital audio data interface having a second input that is connected to said microprocessor interface output.  7. The device according to p. 4, characterized in that it further comprises a clock generator having an input for receiving a clock signal and an output, said DSPC having a second input connected to said output of the clock generator.  8. A method for performing a recursive convolution of a first sequence and a second sequence, characterized in that it includes the steps of: performing an initial convolution; checking whether the step indicator is even; extracting said first sequence from a first memory element; extracting said second sequence from a second memory element; extracting a partial convolution result from the third memory element when said step indicator is even; performing a partial convolution in accordance with the extracted first sequence, the extracted second sequence and the extracted result of the partial convolution; storing the result of partial convolution in the second memory element when the step indicator is even; extracting a partial convolution from the second memory element when the step indicator is odd; performing a partial convolution in accordance with the extracted first sequence, the extracted second sequence and the extracted partial convolution; and storing the result of the partial convolution in the third memory element when said step indicator is odd.  9. The method according to p. 8, characterized in that it further comprises the step of extracting a pre-generated convolution result from the ring buffer.  10 A device for performing block normalization, characterized in that it comprises means for determining a value for receiving a set of values and determining a magnitude of a received value from said set of values and for outputting corresponding value values; an OR gate for receiving said value values, receiving a partial union value, and outputting the next partial union value; and register means for receiving said partial union value and for outputting this partial union value, the final value remaining in said register means determining a normalization coefficient.  11. The device according to p. 10, characterized in that the said means of determining the value contains inverting means for receiving the said set of values and selectively inverting the bits of the said value when the said value is negative; and summing means for adding a single bit to said value with selectively inverted bits when said value is negative.  12. The device according to p. 10, characterized in that it further comprises a shift register for determining the value of the shear normalization in accordance with the said coefficient of normalization and for issuing the said value of the shear normalization; and a multi-register cyclic shift device for receiving said shift normalization value for shifting a second set of values in accordance with said shift normalization value.