JPS62136129A - Test method for analog-digital converter - Google Patents

Test method for analog-digital converter

Info

Publication number
JPS62136129A
JPS62136129A JP27717585A JP27717585A JPS62136129A JP S62136129 A JPS62136129 A JP S62136129A JP 27717585 A JP27717585 A JP 27717585A JP 27717585 A JP27717585 A JP 27717585A JP S62136129 A JPS62136129 A JP S62136129A
Authority
JP
Japan
Prior art keywords
converter
data
frequency
codes
deltaf
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27717585A
Other languages
Japanese (ja)
Inventor
Tadashi Kamei
亀井 正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP27717585A priority Critical patent/JPS62136129A/en
Publication of JPS62136129A publication Critical patent/JPS62136129A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To evaluate simply a conversion error at a high speed by providing a special relation between an input signal frequency fs and a sampling clock frequency fCLK, interleaving an output code of an A/D converter to be tested at an interval of (N-1) codes and comparing two consecutive data strings obtained in this way. CONSTITUTION:The relation of fs=(fCLK/N)+DELTAf (N:1,2,3 and fs>>DELTAf) is held between a sampling clock frequency fCLK and a frequency fs of a continuous period function wave inputted to an A/D converter 3 to be tested, the output codes obtained by the conversion of the A/D converter 3 are interleaved at an interval of (N-1) codes and two consecutive data strings obtained are inputted to a subtractor 7. An error discriminator 8 detects the conversion error by observing the difference of the two conswecutive data from the subtractor 7. The data string being the result of interleaving the output codes at an interval of (N-1) codes becomes a frequency function wave data by one period with a number of fCLK/NDELTAf and beat frequency DELTAf. The value DELTAf is selected so that the difference of two consecutive data at the maximum gradient of the periodic function wave is sufficiently smaller than the allowable calculated conversion error.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、ム/Dコンバータの試験方法に係り。[Detailed description of the invention] Industrial applications The present invention relates to a method for testing a MU/D converter.

特に変換速度が高速なA/Dコンバータの動特性を試験
するのに有効で、なおかつ、試験装置の簡素化及び試験
の高速化を実現するのに有効な方法である。
This method is particularly effective for testing the dynamic characteristics of A/D converters with high conversion speeds, and is also effective for simplifying test equipment and speeding up testing.

従来の技術 従来のA/Dコンバータの動特性試験方法は。Conventional technology What is the conventional dynamic characteristics test method for A/D converters?

第2図に示すように正弦波信号発生器9より正弦波を、
標本化クロック発生器2より標本化クロックを、それぞ
れ、被°試験A/Dコンバータ3のアナログ入力端子3
1.標本化クロック入力端子32に入力し、ディジタル
出力端子33より出力されたディジタル出力コードをバ
ッファメモリ/Qに格納する。得られたデータ列からコ
ンピュータllによってこのデータに最も近い理想正弦
波を算出し、この理想正弦波と実際に変換されたデータ
との誤差から動特性を評価していた。
As shown in FIG. 2, the sine wave signal generator 9 generates a sine wave.
The sampling clock from the sampling clock generator 2 is input to the analog input terminal 3 of the A/D converter 3 under test.
1. A digital output code inputted to the sampling clock input terminal 32 and outputted from the digital output terminal 33 is stored in the buffer memory /Q. An ideal sine wave closest to this data is calculated from the obtained data string by a computer 11, and dynamic characteristics are evaluated from the error between this ideal sine wave and the actually converted data.

発明が解決しようとする問題点 このような試験方法で計算により得られた理想正弦波と
実際に変換されたデータとの誤差からA/Dコンバータ
の変換精度を評価することはできるが計算に使用される
サンプルデータ数は少なく、被試験人/Dコンバータを
入力信号と標本化クロック間のあらゆる条件に対し十分
評価しているとはNいがたく、コンピュータによる計算
にもかなりの時間を要する。また、高精度の正弦波発生
器や高速バッファメモリ、演算用コンピュータを必要と
し試験装置が犬がかりなものとなっている。
Problems to be Solved by the Invention Although it is possible to evaluate the conversion accuracy of an A/D converter from the error between the ideal sine wave obtained by calculation and the actually converted data using such a test method, it is not possible to use it for calculation. The number of sample data to be analyzed is small, it is difficult to fully evaluate the test subject/D converter against all conditions between the input signal and the sampling clock, and calculations by a computer require a considerable amount of time. In addition, the test equipment is complicated because it requires a high-precision sine wave generator, a high-speed buffer memory, and a computing computer.

本発明は、上記の点に鑑み変換されたディジタル出力コ
ードをリアルタイムで大量に処理してA/Dコンバータ
の変換精度を評価し、がっ、試験装置の構成において高
精度の正弦波発生器や高速バッファメモリ、演算用コン
ピュータを必要とせず試験の高速化を実現しうる試験方
法を提供するものである。
In view of the above points, the present invention evaluates the conversion accuracy of an A/D converter by processing a large amount of converted digital output codes in real time. The present invention provides a test method that can speed up testing without requiring a high-speed buffer memory or a computer for calculation.

問題点を解決するだめの手段 本発明は、上記問題点を解決するために被試験用人/D
コンバータに入力する連続な周期関数波(fs:>Δf
)なる関係を持たせ、前記A/Dコンバータにより変換
して得られた出力コードから(N−1)個置きに抜き取
り、得られたデータ列の連続した2データを比較するス
テップをもつものである。
Means for Solving the Problems In order to solve the above problems, the present invention provides
Continuous periodic function wave (fs:>Δf) input to the converter
), extracting every other (N-1) code from the output code obtained by conversion by the A/D converter, and comparing two consecutive pieces of data in the obtained data string. be.

作用 このとき得られるデータ列は、入力信号周波数で一周期
分が構成される。ここでΔfを周期関数波の最大傾斜部
において連続した2デ一タ間の差が、計算上許容変換誤
差より十分小さい値(0,1LSB以下程度)になるよ
う選択することにより、得られたデータ列の連続した2
データを比較してその差を求め人/Dコンバータの動特
性を評価しようとするものである。そして1本発明では
、(N−1)個置きに得られたデータ列の連続した2デ
ータを比較するだけでム/Dコンバータの評価を行なう
ことができるため簡単なハードロジックで実現でき、リ
アルタイムで処理するため、わずかな時間で大量の出力
データを処理することができる。また1人力信号の波形
品位も要求されない。
Effect: The data string obtained at this time consists of one period at the input signal frequency. Here, by selecting Δf so that the difference between two consecutive data at the maximum slope part of the periodic function wave is a value sufficiently smaller than the calculation-allowable conversion error (approximately 0.1 LSB or less), Two consecutive data columns
The purpose is to compare the data and find the difference to evaluate the dynamic characteristics of the human/D converter. In addition, in the present invention, it is possible to evaluate the MU/D converter by simply comparing two consecutive data strings obtained every (N-1) times, so it can be realized with simple hardware logic, and in real time. A large amount of output data can be processed in a short amount of time. Furthermore, the waveform quality of a single-handed signal is not required.

実施例 第1図に本発明の一実施例を示す。第1図において1は
周期関数波発生器、2は標本化クロック発生器である。
Embodiment FIG. 1 shows an embodiment of the present invention. In FIG. 1, 1 is a periodic function wave generator, and 2 is a sampling clock generator.

3は被試験A/Dコンバータであり、アナログ信号入力
端子31.標本化クロック入力端子32を有し、変換さ
れた出力コードはディジタル出力端子33より出力され
る。4は出力コードを(N−1)個置きに抜き取るだめ
のクロックを発生させるX分周器であり、5のラッチ人
と6のラッチBに供給される。ラッチ人5の入力ニハ、
ム/Dコンバータ3の出力が、ラッチB60入力にはラ
ッチ人5の出力が接続されているため、ラッチB6には
必ずラッチムロの1クロツク前のデータがセットされる
。従って、減算器7には常時A/Dコンバータ3の出力
コードを(N−1)個置きに抜き取ったデータ列の連続
した2データが入力され、その差を観測することにより
誤差判定器8で変換誤差を検出することができる。
3 is an A/D converter under test, which has analog signal input terminals 31. It has a sampling clock input terminal 32, and the converted output code is outputted from a digital output terminal 33. 4 is an X frequency divider which generates a clock for extracting every (N-1) output code, and is supplied to latch 5 and latch B 6. Latch person 5 input niha,
Since the output of the system/D converter 3 and the output of the latch operator 5 are connected to the input of the latch B60, data one clock before the latch input is always set in the latch B6. Therefore, the subtracter 7 is always input with two consecutive data strings obtained by extracting every (N-1) output code from the A/D converter 3, and by observing the difference, the error determiner 8 Conversion errors can be detected.

+Δf (N:1.2.3・・−・・)(fs>Δf)
なト周波数Δfの一周期分の周波関数波データとなる。
+Δf (N: 1.2.3...) (fs>Δf)
This becomes frequency function wave data for one period of frequency Δf.

Hの値は、人/Dコンバータ3の性能によりfsとf。The value of H depends on fs and f depending on the performance of the human/D converter 3.

□の関係から最適値を選択し、Δfの値は5周期関数波
の゛最大傾斜部の連続した2データの差を計算上許容変
換誤差より十分小さい値(o、1LsB以下程度)にな
るよう選ぶ。例えば1mピットのム/Dコンバータにダ
イナミックレンジいっばいの正弦波を入力したとすると
最大傾斜部における連続した2デ一タ間の差は、り間の
差は、変換誤差がなければ必ず±1LsB以下になるは
ずであり、その差を観測することによりム/Dコンバー
タ3の変換誤差を検出できる。
Select the optimal value from the relationship □, and set the value of Δf so that the difference between two consecutive data of the maximum slope part of the 5 periodic function waves is sufficiently smaller than the allowable conversion error (o, about 1LsB or less). choose. For example, if a sine wave with the full dynamic range is input to a 1 m pit Mu/D converter, the difference between two consecutive data points at the maximum slope will be ±1 LsB unless there is a conversion error. The conversion error of the MU/D converter 3 can be detected by observing the difference.

本実施例における入力信号は、その最大傾斜部の傾きの
み重要で波形品位には影響されない。従って、被試験用
ム/Dコンバータの入力ダイナミックレンジを越えて入
力しても何ら問題ない。
For the input signal in this embodiment, only the slope of the maximum slope part is important and is not affected by the waveform quality. Therefore, there is no problem even if the input exceeds the input dynamic range of the M/D converter under test.

発明の効果 以上述べてきたように1本発明によればIA/Dコンバ
ータのAC信号入力時の変換誤差を簡単にしかも高速に
評価することができ実用的にきわめて有用である。
Effects of the Invention As described above, according to the present invention, it is possible to easily and quickly evaluate the conversion error when an AC signal is input to an IA/D converter, and it is extremely useful in practice.

【図面の簡単な説明】 第1図は本発明の一実施例における人/Dコンバータの
動特性試験装置のブロック図、第2図は従来の試験装置
のブロック図である。 1・・・・・・周期関数発生器、2・・・・・・標本化
クロック発生器、3・・・・・・被試験A/Dコンバー
タ、31・・・・・・アナログ信号入力端子、32・・
・・・・標本化クロック入力端子133・・・・・・デ
ィジタル信号出力端子。 4・・・・・・y分周器、6・・・・・・ラッチム、6
・・・・・・ラッチB、7・・・・・・減算器、8・・
・・・・誤差判定器、9・・・・・・正弦波信号発生器
、10・・・・・・バッファメモリ、11・・・・・・
コンピュータ。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第2
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a dynamic characteristic testing device for a human/D converter according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional testing device. 1... Periodic function generator, 2... Sampling clock generator, 3... A/D converter under test, 31... Analog signal input terminal , 32...
... Sampling clock input terminal 133 ... Digital signal output terminal. 4...y frequency divider, 6...latchim, 6
...Latch B, 7...Subtractor, 8...
...Error judger, 9...Sine wave signal generator, 10...Buffer memory, 11...
Computer. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
figure

Claims (1)

【特許請求の範囲】[Claims] 被試験用A/Dコンバータに入力する連続な周期関数の
入力信号周波数f_Sと標本化クロック周波数f_C_
L_Kとの間にf_S=(f_C_L_K/N)+Δf
(N:1、2、3・・・・・・)(f_S≫Δf)なる
関係を持たせ、前記被試験用A/Dコンバータで変換さ
れたディジタル出力コードを(N−1)個置きに抜き取
り、得られたデータ列の連続した2データを比較するこ
とを特徴とするA/Dコンバータの試験方法。
Input signal frequency f_S of continuous periodic function input to the A/D converter under test and sampling clock frequency f_C_
f_S=(f_C_L_K/N)+Δf between L_K
(N: 1, 2, 3...) (f_S≫Δf), and every (N-1) digital output codes converted by the A/D converter under test are 1. A test method for an A/D converter, which comprises comparing two consecutive pieces of data obtained by extracting data.
JP27717585A 1985-12-10 1985-12-10 Test method for analog-digital converter Pending JPS62136129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27717585A JPS62136129A (en) 1985-12-10 1985-12-10 Test method for analog-digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27717585A JPS62136129A (en) 1985-12-10 1985-12-10 Test method for analog-digital converter

Publications (1)

Publication Number Publication Date
JPS62136129A true JPS62136129A (en) 1987-06-19

Family

ID=17579853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27717585A Pending JPS62136129A (en) 1985-12-10 1985-12-10 Test method for analog-digital converter

Country Status (1)

Country Link
JP (1) JPS62136129A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02101821A (en) * 1988-10-11 1990-04-13 Sony Corp Digital error detection circuit
JPH04231883A (en) * 1990-05-25 1992-08-20 American Teleph & Telegr Co <Att> Method and apparatus for testing delta-sigma modulator
JPH05291952A (en) * 1990-03-15 1993-11-05 American Teleph & Telegr Co <Att> Built-in self test for a/d converter
US7688239B2 (en) 2007-03-20 2010-03-30 Denso Corporation Fault detection apparatus for detecting failure of A/D converter due to loss of externally supplied clock signal

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58172560A (en) * 1982-04-02 1983-10-11 Fujitsu Ltd Linearity measurement of d/a converter
JPS58174861A (en) * 1982-04-07 1983-10-13 Sony Tektronix Corp Property measuring apparatus for analog/digital converter
JPS60248023A (en) * 1984-05-23 1985-12-07 Rohm Co Ltd Characteristic measuring device for analog/digital converter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58172560A (en) * 1982-04-02 1983-10-11 Fujitsu Ltd Linearity measurement of d/a converter
JPS58174861A (en) * 1982-04-07 1983-10-13 Sony Tektronix Corp Property measuring apparatus for analog/digital converter
JPS60248023A (en) * 1984-05-23 1985-12-07 Rohm Co Ltd Characteristic measuring device for analog/digital converter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02101821A (en) * 1988-10-11 1990-04-13 Sony Corp Digital error detection circuit
JPH05291952A (en) * 1990-03-15 1993-11-05 American Teleph & Telegr Co <Att> Built-in self test for a/d converter
JPH04231883A (en) * 1990-05-25 1992-08-20 American Teleph & Telegr Co <Att> Method and apparatus for testing delta-sigma modulator
US7688239B2 (en) 2007-03-20 2010-03-30 Denso Corporation Fault detection apparatus for detecting failure of A/D converter due to loss of externally supplied clock signal

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