JPS6387952U - - Google Patents
Info
- Publication number
- JPS6387952U JPS6387952U JP18266186U JP18266186U JPS6387952U JP S6387952 U JPS6387952 U JP S6387952U JP 18266186 U JP18266186 U JP 18266186U JP 18266186 U JP18266186 U JP 18266186U JP S6387952 U JPS6387952 U JP S6387952U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- frequency
- counter
- synchronization signal
- pulses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 230000010355 oscillation Effects 0.000 claims 3
- 238000009499 grossing Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Details Of Television Scanning (AREA)
Description
第１図は本考案の偏向制御用電圧作成回路を概
略的に示すブロツク図、第２図は第１図の回路構
成の一実施例を示すブロツク図、第３図は第２図
の具体的回路の一例を示す回路図、第４図は従来
のＦ／Ｖ変換回路を示す回路図である。
１１…周波数逓倍回路、１２…Ｆ／Ｖ変換回路
、２１…クロツク発振器、２２…第１のカウンタ
、２３…第２のカウンタ、２４…ラツチ、２５…
第３のカウンタ。
FIG. 1 is a block diagram schematically showing the deflection control voltage generation circuit of the present invention, FIG. 2 is a block diagram showing an embodiment of the circuit configuration of FIG. 1, and FIG. 3 is a concrete example of the circuit configuration of FIG. A circuit diagram showing an example of the circuit, FIG. 4 is a circuit diagram showing a conventional F/V conversion circuit. DESCRIPTION OF SYMBOLS 11... Frequency multiplier circuit, 12... F/V conversion circuit, 21... Clock oscillator, 22... First counter, 23... Second counter, 24... Latch, 25...
Third counter.
Claims (1)
めの回路であつて、クロツクパルスを発生するク
ロツク発振回路と、このクロツク発振回路からの
クロツクパルスを１／ｎ（ｎは正の整数）に分周
する第１のカウンタと、前記同期信号のタイミン
グでリセツト可能にされ前記第１のカウンタから
の分周パルスをカウントしてバイナリーデータを
得る第２のカウンタと、この第２のカウンタから
のバイナリーデータを前記同期信号のタイミング
でラツチするラツチと、プリセツト機能を有し前
記ラツチに保持されたバイナリーデータをプリセ
ツト入力する一方前記クロツク発振回路からのク
ロツクパルスをカウントすることにより、前記同
期信号の周波数のｎ倍のパルス出力を得る第３の
カウンタとから構成される周波数逓倍回路と、 この周波数逓倍回路で逓倍したパルスを直流電
圧に変換し、前記同期信号周波数に比例した制御
電圧を出力するＦ／Ｖ変換回路とを具備したこと
を特徴とする偏向制御用電圧作成回路。 (2) 前記Ｆ／Ｖ変換回路は、前記周波数逓倍回
路からの第３のカウンタからのパルスを入力し、
前記同期信号周波数に比例した一定幅のパルスに
交換する単安定マルチバイブレータと、この単安
定マルチバイブレータからのパルス電圧を平滑し
、直流電圧に変換する平滑回路とから構成される
ことを特徴とする実用新案登録請求の範囲第１項
記載の偏向制御用電圧作成回路。 (3) 前記周波数逓倍回路の第３のカウンタにお
ける最上位データ入力端子に常時ハイレベルのデ
ータを入力するようにしたことを特徴とする実用
新案登録請求の範囲第１項記載の偏向制御用電圧
作成回路。[Claims for Utility Model Registration] (1) A circuit for multiplying the frequency of an input synchronizing signal, which includes a clock oscillation circuit that generates clock pulses, and a clock pulse from this clock oscillation circuit that is multiplied by 1/n (n is a positive integer); a second counter that is resettable at the timing of the synchronization signal and obtains binary data by counting the frequency-divided pulses from the first counter; A latch that latches the binary data from the second counter at the timing of the synchronization signal, and a preset function, inputs the binary data held in the latch as a preset while counting clock pulses from the clock oscillation circuit. , a third counter that obtains a pulse output n times the frequency of the synchronization signal, and a frequency multiplication circuit that converts the multiplied pulses into a DC voltage proportional to the frequency of the synchronization signal. 1. A deflection control voltage generation circuit comprising: an F/V conversion circuit that outputs a control voltage. (2) The F/V conversion circuit inputs a pulse from a third counter from the frequency multiplication circuit,
It is characterized by being comprised of a monostable multivibrator that exchanges pulses with a constant width proportional to the synchronization signal frequency, and a smoothing circuit that smoothes the pulse voltage from this monostable multivibrator and converts it into a DC voltage. A voltage generation circuit for deflection control according to claim 1 of the utility model registration claim. (3) The deflection control voltage according to claim 1 of the utility model registration claim, characterized in that high level data is always input to the highest data input terminal of the third counter of the frequency multiplier circuit. Create circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18266186U JPS6387952U (en) | 1986-11-26 | 1986-11-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18266186U JPS6387952U (en) | 1986-11-26 | 1986-11-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6387952U true JPS6387952U (en) | 1988-06-08 |
Family
ID=31128667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18266186U Pending JPS6387952U (en) | 1986-11-26 | 1986-11-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6387952U (en) |
-
1986
- 1986-11-26 JP JP18266186U patent/JPS6387952U/ja active Pending
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