JPS6387924U - - Google Patents

Info

Publication number
JPS6387924U
JPS6387924U JP18359286U JP18359286U JPS6387924U JP S6387924 U JPS6387924 U JP S6387924U JP 18359286 U JP18359286 U JP 18359286U JP 18359286 U JP18359286 U JP 18359286U JP S6387924 U JPS6387924 U JP S6387924U
Authority
JP
Japan
Prior art keywords
circuit
clock
ring counter
divide
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18359286U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18359286U priority Critical patent/JPS6387924U/ja
Publication of JPS6387924U publication Critical patent/JPS6387924U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)
JP18359286U 1986-11-28 1986-11-28 Pending JPS6387924U (US07709020-20100504-C00041.png)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18359286U JPS6387924U (US07709020-20100504-C00041.png) 1986-11-28 1986-11-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18359286U JPS6387924U (US07709020-20100504-C00041.png) 1986-11-28 1986-11-28

Publications (1)

Publication Number Publication Date
JPS6387924U true JPS6387924U (US07709020-20100504-C00041.png) 1988-06-08

Family

ID=31130474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18359286U Pending JPS6387924U (US07709020-20100504-C00041.png) 1986-11-28 1986-11-28

Country Status (1)

Country Link
JP (1) JPS6387924U (US07709020-20100504-C00041.png)

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