JPS6386923A - Syndrome generating circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale used for an optical card, a magnetooptical disk, a DAT, by multiplying an output of an EXOR circuit by alpha (m) times and latching each output thereof the a register by different clocks, in an encoding/decoding circuit in a field for correcting an error. CONSTITUTION:Syndromes S0-S3 are constituted of a bus line, and a clock CK and an OE (output enable) are used so as to complete with each other among the syndromes S0-S3. Therefore, the clock and the OE used for each of the syndromes S0-S3 are controlled by a signal shown in the figure. The clocks CKB1, 3, 5 and 7 are inversion signals H L and L H of CK1, 3, 5 and 7. In this way, as for an input J, it is necessary to input it in synchronism with the clock CK1 at every ji. Also, SCL is a signal which becomes L, when a first receiving word j1 is inputted. In this way, in a syndrome S, its S0-S3 are outputted at every four periods, and at every SCL, the final answer is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to the field of error correction, and particularly to a syndrome generation circuit required in a BCH code encoding/decoding circuit.

[Prior art]

When a received word J expressed by equation (2) in which an error E is added to a code word I is received, the decoder first generates a syndrome S. The syndrome is expressed in the case of double error correction coding (
1) It is generated by multiplying the parity check matrix H expressed by Equation 1 and the received word J. It can be seen from equation (3) that the syndrome generated in this manner is the product of check matrix H and error E.

Usually, the syndrome generation circuit calculates 3 1=αl'1n-11,jl +αl+n-21・for each Si.
j 2+...+α・jn−1+jn Fuji (((α1 ・ jl) + j2) ・ α′)
＋・ ・ ・ jn−1) ・ αl +J n
Therefore, the circuit on the Galois field GF (2Q) can be constructed as shown in Fig. 1. Here, the α1 circuit is the second
This can be realized by stacking i stages of α circuits in Figure 2 (primitive polynomial p(x)=xa+x4 +x3 +x2+
1). Therefore, in order to realize SO to S3 expressed by equation (1), the configuration is as shown in FIG. Here C
K is cj2ock for each received word ji, and CL is cnear for each code length.

In the configuration of FIG. 3B, the circuit configuration becomes obviously large when q is large or when i of St is large. Also, SO~
This is inconvenient when processing is performed by connecting S3 with a pass line.

Decoder However, the presence or absence of errors can be determined by generating syndromes. It can be determined that

...(2) Therefore, the syndrome S is S+H-J=H according to equation (3).
・(1+E)=H-1 Here, there is an error e in the positions of i and j.
i and ejl) is expressed as the product of syndrome generation error E and check matrix H.

(From equation (1)) +H-E=H-E Consider the case where (3) exists.

〔the purpose〕

In order to eliminate the drawbacks of the above-mentioned conventional example, the present invention reduces the circuit scale of the syndrome generation circuit as much as possible, and
It is an object of the present invention to provide a syndrome generation circuit that facilitates the pass line configuration of SO to S3.

Another object of the present invention is to provide a miniaturized device such as an optical disk equipped with the circuit.

(Example) Hereinafter, with reference to the above-mentioned formula and drawings, the present invention will be described.
Explain in detail. Previously, the applicant filed patent application No. 60-7967.
Since we have filed an application regarding error correction under 4.
Details are omitted.

FIG. 4 is a diagram showing the circuit configuration of the present invention.

The circuit in Figure 4 does not require creating each α1 circuit separately.
1) The root α1 of the BCH code in the equation is α1 (r: arbitrary, here rzo is used) to αr+1. By using α12 and successive advancement, the circuit scale can be reduced and SO~S
3 in a pass line configuration. Since SO to S3 have a pass line configuration, CK and OE (output enable) must be used in opposition between 5o and 33. Therefore, CK and OE used for each of SO to S3
is controlled by the signals shown in FIG. Furthermore, CKBI,
3, 5.7 is the inverted signal of CK1, 3° 5.7 H→LL-
H). Therefore, the input J is CK every ji
It is necessary to input in synchronization with I. Further, SCL is a signal that becomes L when the first received word j1 is manually input. As a result, SO to S3 are output every 4 cycles in S.
A final answer is generated for each CL.

However, 5PCL is always H in decoding.

The above equation (1) is calculated using digital Fourier transform DFT.
It can also be applied to the problem of

In addition, when multiplying by α1 in advance, it is sufficient to place an α1 circuit between the register that outputs J and EXOR.

Or, αr- between the register that outputs J and EXOR
J, the circuit (any positive number to 1), and EXOR,
The α2 circuit may be placed before the So register and the α circuit. Next, FIG. 6 shows a case where α1 is required. The α8 circuit can be realized by stacking the α circuits shown in FIG. 2 in X stages.

(Effect) As explained above, with the configuration of the present invention, the Galois field G
When 1 of F (2') is large, or when there are many i of syndrome Si, or when connecting syndromes St with each pass line, while reducing the circuit scale,
The above can be achieved.

As described above, by using the circuit of the present invention in optical disks, optical cards, magneto-optical disks, and DATs, devices can be extremely miniaturized.

[Brief explanation of the drawing]

Figure 1 shows the syndrome Si generation circuit. Figure 2 shows α
FIG. 3 shows a conventional syndrome generation circuit. FIG. 4 shows a syndrome generation circuit of the present invention. FIG. 5 shows timing signals. FIG. 6 shows another example of the syndrome generation circuit of the present invention. Figure CK showing an example - Clock

Claims (2)

[Claims] (1) When performing the following operations on the Galois field, ▲ There are mathematical formulas, chemical formulas, tables, etc. ▼ m registers and their outputs are configured as a bus line, and the input j_1 is multiplied by α^r in advance. A syndrome characterized by having one r circuit and one EXOR circuit for EXORing their outputs, multiplying the output by α m times, and latching each output in the above-mentioned register with a different clock. generation circuit. (2) When performing the following operations on the Galois field, ▲ There are mathematical formulas, chemical formulas, tables, etc. ▼ m registers that are cleared in synchronization with j_1 and input j_1 (i = 1・-n) EXO
Claim 1, characterized in that it has one circuit for R, multiplies its output by α m times, and latches each output in the m registers with different clocks. Syndrome generation circuit.