JPS6386007A - Power-down/reset signal generating circuit for microcomputer - Google Patents

Abstract

PURPOSE:To prevent the malfunctions of a CPU by applying the power-down signals to the CPU as well as to a single input of a reset signal generating circuit that is backed up by a back-up power supply. CONSTITUTION:A commercial power supply is rectified by a power supply circuit 1 and applied to a CR circuit consisting of a capacitor 2 and a resistance 3. When the voltage of the CR circuit exceeds the sum of value voltage level of a Zener diode 4 and the base-emitter voltage level of a transistor (Tr)5, this Tr5 is turned on and at the same time a TR6 is also turned on. Thus the power-down signal is changed to a high level from a low level. This power- down signal is applied to the clock of an FF7 and a Tr12 is turned on to set the reset signal at a high level. While a CPU starts to monitor the power-down signal when this signal is set at a low level decides a power supply OFF state. The CPU is held when the power supply is cut. In this case, the output of a gate 11 is applied to the reset terminal R of the FF7 and the Tr12 is turned off to set the reset signal at a low level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] January Mizumoto relates to a reset signal generation circuit used in a CPU of a micro combi coater.

[Prior Art] For example, the circuit shown in Fig. 3 has been conventionally used as a reset signal circuit for the CPU of a microcomputer, and the time chart of the signals of this circuit is shown in Fig. 4. . That is, from the waveform shaping circuit 13, 'rI
A pulse voltage having a frequency equal to the i source frequency is applied to the ridger one-shot generation circuit 14, and if the AC power supply continues to be cut off for a certain period of time, the circuit 1
One pulse is generated from 4, and this signal is output as a power down signal. At the same time, the generated signal applied to the one-shot output generation circuit 15 and the signal from the rising reset generation circuit 1G are sent to the CPU via the gate 17.
Gives a reset signal when the i source falls.

[Problems to be Solved by the Invention] The above-mentioned prior art has the following problems. Since the rising reset signal generation circuit is operated by an AC power supply, if there is chattering when the power is turned on, the level of the reset signal will become unstable. - On the other hand, since the power supply for the CPU is also obtained by rectifying alternating current, it becomes unstable due to chattering. In this case, if the power supply voltage of the CPU rises to a level that activates the CPU and the level of the reset signal exceeds the reset voltage, the CPU will not be initially reset and will malfunction. In addition, commercial power supplies have instantaneous interruptions, noise, etc., and these are smoothed out by capacitors.
There are some cases in which no abnormality occurs in a.

Even in such a case, a circuit with only the above circuit configuration (hardware) may generate a reset signal during normal operation and cause the CPLJ to perform power-off processing.

[Means and actions for solving the problem] A power down signal generated in a hardware circuit is added to the input of the CPU, and is also added to one input of a reset signal generation circuit backed up by a backup power supply, while the output signal of the CPU is is added to other inputs of the reset signal generating circuit to generate a reset signal.

The reset signal generation circuit backed up by a backup power supply is one that releases the reset signal at the rise of the power down signal. For the power down signal, supply the OR circuit with DC obtained by rectifying the AC power supply, and set it to a high level when the voltage of the OR circuit exceeds the threshold.The reset signal will always be at a constant level for a certain period of time after the power is turned on. It can be maintained below and malfunctions do not occur when the power is turned on. In addition, the power down signal is monitored by the CPU and
Since the reset signal can be generated based on the determination, it is possible to avoid generation of unnecessary reset signals when the power supply is momentarily cut off or the like.

[Example] Hereinafter, an example of an eggplant according to the present invention will be described with reference to FIGS. 1 and 2. Commercial power is rectified by a power supply circuit 1 and applied to an OR circuit constituted by a capacitor 2 and a resistor 3. When the voltage of the OR circuit, which rises with a certain time constant when the power is turned on, exceeds the sum of the Zener voltage of the Zener diode 4 and the base-emitter voltage of the transistor 5, the transistor 5 turns on, and therefore the base current of the transistor 6 increases. begins to flow, and transistor 6 is also turned on. At this time, the power down signal changes from low to high. A power down signal is also applied to the clock of flip-flop 7. The flip-flop 7 is of a type in which when the R1S terminal is high, the inversion of the D input is output to the Q at the rising edge of the clock, and is connected to a battery backup power source. As will be described later, the output of the 7-lip-flop 7 is high when the power supply falls, so the D input is always high. The d output of the flip-flop 7 falls at the rise of the aforementioned power down signal. At this time, the transistor 12 is turned on and the reset signal becomes high, but before that, the Q output is maintained at a high state above a certain level, so the reset signal remains constant regardless of the value of the emitter voltage of the transistor 12. It becomes possible to provide a reliable rising reset signal to the CPLI.

Next, the generation of the reset signal at the power station will be described. When the power is turned off, the power down signal becomes low after a delay time determined by the time constant of the OR circuit, the Zener voltage, and the base-emitter voltage, but since the flip-flop 7 is of the type that operates with a rising clock, does not change.

A power-down signal is applied to the interrupt input and other input terminals of the CPLI, and when the power-down signal becomes low, the CPU starts monitoring the power-down signal and determines power-off according to the program. If the CPU determines that the power is off, it performs necessary processing and then sets the reset command signal, which is the output of the CPU, to low, thereby placing the CPU in a hold state. Therefore, the CPU stop signal indicating the hold state of the CPU also becomes low.

At this time, the output of gate 11 changes from high to low,
This differential value is applied to the reset terminal R of the flip-flop 7 via the capacitor 10. Since the voltage of Vcc is applied to the terminal R via the resistor 8, it is always high.
Two pulses are applied only when the output of gate 11 changes from high to low.

When the flip-flop 7 is reset in this way, the Q output becomes high, the transistor 12 is turned off, and the reset signal becomes low. Therefore, to the CPU? ff power disconnection 0
A falling reset signal can be given. Note that when the R terminal of the diode 9 in the figure is at the Vcc level,
This is provided to prevent a voltage higher than Vcc from being applied to the R terminal when the output of the gate 11 changes from low to high.

Also, vcCl is the i-system power supply, which goes down after a certain period of time has passed after the power is cut off, and VBAT is a backup power supply using a battery, and its level remains unchanged even if the power is cut off.

[Effects of the Invention] According to the present invention, since the rising reset signal is ensured to be below a certain level, there is no malfunction of the CPLI at the rising edge. Furthermore, since the CPU monitors the power down signal at the time of falling and makes a judgment to generate the reset signal, it is possible to avoid generating a falling reset signal for unnecessary power cut-off in the event of a momentary power outage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a time chart of signals in the same circuit, FIG. 3 is a block diagram of a reset signal generation circuit according to the prior art, and FIG. 4 is a diagram of signals in the same circuit. This is a time chart. In the figure, 1 is a rectifier circuit, 2.10 is a capacitor, 3.8 is a resistor, 4 is a Zener diode, 5.6.12 is a transistor, 7 is a flip 70 tube, 9 is a diode, and 11 is a gate. Patent applicant: Fujitsu General Ltd. Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] In addition to the input of a power down signal generation circuit which sets the output voltage to a high level when the voltage obtained by rectifying the AC power supply through the CR circuit exceeds a predetermined threshold value, the output of the power down signal generation circuit is also provided. A signal is applied to the input of the CPU and one input of a reset signal generation circuit backed up by a backup power supply, while an output signal of the CPU is applied to the other input of the reset signal generation circuit. A power-down signal and reset signal generation circuit for a microcomputer, characterized in that the output is used as a CPU reset signal directly or via an interface circuit.