JPS6384318A - Counter circuit - Google Patents

Abstract

PURPOSE:To test whether or not all digits are normally counted in a short period by providing a 1st and 2nd control circuits and counting all digits in a test mode. CONSTITUTION:The 1st control circuits 10-12 control the counting actions of counters 1-3 with a test mode setting signal 60 and the carry signals 81-83 received from the lower digit counters. These circuits 10-12 are connected to the counters 1-3 excluding a counter 4 for the lowest digit and consist of exclusive OR gates 10-12, for example. While the counter 4 is connected with a delay circuit 20 which delays the carry signal 83 by one clock and the 2nd control circuit 21 which controls the counting action of the counter 4 with the carry signal delayed by one clock and a setting signal 60. The circuit 21 consists of a NAND gate 21, for example. Thus it is possible to check whether all digits are normally counted or not in a short period.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to counter circuits, and in particular, to a multi-digit counter circuit built into an LSI, and a counter with an improved method for testing whether the operation is being executed normally. Regarding circuits.

〔overview〕

The present invention sets a test mode using a test mode setting signal in a counter circuit configured by cascading a plurality of multi-bit counters, and enables all digit counters to operate in this test mode. For counters other than digits, when a carry signal from the lower digit is generated, the counting operation is stopped and the generation of the carry signal is confirmed, and for the counter at the lowest digit, the carry signal from the own counter is delayed by one increment. By stopping the counting operation, it is possible to test whether the counting operation of all digits is being executed normally in a short period of time.

[Conventional technology]

In conventional counter circuits of this type, their operation can be tested by either not providing a test mode and testing whether the counter circuit is operating normally by performing normal counting operations, or by providing a test mode and testing the counter circuit. They divided it up and tested each digit to see if it was working properly.

[Problem that the invention seeks to solve]

The operation test method for the conventional counter circuit described above is as follows:
The reason why a normal counting operation is executed without providing a test mode is when a counter is configured with multiple digits, for example, when a counter is connected to one digit by 4 bits, it is necessary to perform a normal counting operation for all digits. requires a 24" clock input. Therefore, it has the disadvantage of requiring a very large amount of time.

In addition, the method of providing a test mode and testing each digit separately has the disadvantage that it is not possible to confirm the carry across the division units, and the test mode must be reset for each division unit.

That is, conventional counter circuits have the disadvantage that when the number of digits increases, it becomes difficult to test their operation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a counter circuit that can easily and accurately perform operational tests by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides a counter circuit configured by cascading a plurality of multi-bit counters, in which each counter except the lowest digit counter receives a test mode setting signal and a carry signal from the lower digit counter. A first control circuit for controlling the counting operation is connected, and the lowest digit of the counter circuit has a delay circuit that delays the carry signal output from the self-blade counter by one clock, and a delay circuit that delays the carry signal output from the self-blade counter by one clock. The present invention is characterized in that it is connected to a second control circuit that controls the counting operation based on the carry signal and the test mode setting signal.

Preferably, the first and second control circuits are configured to stop the counting operation of the connected counter when the carry signal is input.

[Effect]

For example, a two-man exclusive OR gate is used as the first control circuit, the test mode setting signal and the carry signal from the lower digit counter are connected, and all the counters are operated by the cross/7 signal. As a result, when a carry signal is generated from a lower digit counter, that counter stops counting, so it can be confirmed whether the carry signal is correctly generated for counters other than the lowest digit counter. A Nant gate, for example, is used as the second control circuit, and the test mode signal and a carry signal obtained by delaying the carry signal from the own counter by one clock via a delay circuit are connected. In this way, the lowest digit counter stops its counting operation one clock later than the other counters, which prevents all the counters from stopping their counting operations at the same time and allows continuous execution of counting operations.

Therefore, it is possible to test whether the counting operation of all digits is normally executed in a short time.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

This embodiment consists of four counters 1, 2, 3 and 4 which are configured with n bits and are connected in cascade, and each counter 1.
．． two-man exclusive-or gates 10.11 and 12 which generate count enable signals for counter 4 and input them to their count enable inputs; and a two-man power Nantes which generates a count enable signal of counter 4 and inputs them to its count enable inputs. gate 21 and a flip-flop 20 that delays the carry signal 83 of the counter 4 by one clock.
Contains. A clock signal 50 for executing a counting operation is connected to each counter 1.2.3 and 4, and a test mode setting signal 60 is connected to one input of each of exclusive OR gates 10.11 and 12 and NAND gate 21. The carry signal 83 output from the counter 4 is connected to the other input of the exclusive OR gate 12, and the carry signal 82 output from the counter 3 is connected to the other input of the exclusive OR gate 11, and the carry signal 83 output from the counter 4 is connected to the other input of the exclusive OR gate 12.
The carry signal 81 output from the exclusive OR gate 10
The carry signal 80 is output from the counter 1. Additionally counters 1.2.3 and 4
and flip-flop 20 each receive a reset signal 70.
is connected to the input of the flip-flop 20, and the carry signal 83 of the counter 4 is connected to the input of the flip-flop 20.
The output of the carry signal 84 delayed by one clock is connected to the other input of the Nant gate 21. Note that here, counter 1 constitutes the highest digit, and counter 4 constitutes the lowest digit.

The feature of the present invention is that, in FIG. 1, exclusive OR gates 0.11 and 12 are used as a first control circuit, a flip-flop 20 is used as a delay circuit, and a Nant gate 21 is used as a second control circuit. This is because it was established.

Next, the operation of this embodiment will be explained with reference to the operation timing chart shown in FIG. Note that in FIG. 2, m indicates the maximum value of an n-bit counter.

When reset signal 70 is initially activated, counter 1.
2.3 and 4 are all cleared to the "0" level. Test mode signal 60 is then activated, and when clock signal 50 is activated, exclusive OR gates 10.11 and 12
Since the output of is “1” level, counters 1, 2 and 3
performs a count. Also, since the flip-flop 20 of the Nant gate 21 is not sent, the output is "1".
level, and the counter 4 also performs a power-down operation.

When the count progresses and the count reaches the maximum value (all output bits of the counter are at the 11" level), a carry signal 83 is generated from the lowest digit of the counter 4, and the output of the exclusive OR gate of the next digit is set to the "0" level. shall be. Then, the counting operation of the next digit counter 3 is stopped and the carry signal 8 is output.
The output of 2 is also suppressed. Therefore, the counter 2 of the next digit is enabled to count because the output of the exclusive OR gate is at the "1" level, and also generates the carry signal 81.

Therefore, the output of the exclusive OR gate 10 of the next highest digit of the counter goes to the "0" level and the counting operation of the counter is inhibited.

As described above, the counter every other digit becomes operable.

Then, in the next clock, the lowest digit counter 4 is
Because of the carry signal 84 delayed by one clock, the output of the Nant gate 21 goes to the "0" level and the counting operation is inhibited. Further, since the outputs of the counter 4 at the lowest digit are all at the "0" level, there is no carry signal 83, and the counter 3 at the next digit performs a counting operation and generates a carry signal 82. Therefore, in the counter 2 of the next digit, the output of the exclusive OR gate becomes "0" level, and the counting operation is inhibited.

As described above, at the next clock, the counters that were operating one clock cycle ago stop operating, and the counters that stopped operating one clock cycle ago start operating.

As explained above, after two clocks when the count reaches its maximum value, all the outputs go to the "0" level, and one cycle of counting is completed.

In this circuit, when the test mode setting signal 60 is not activated, the lowest digit can always be counted, and the other digits can be counted when a carry signal is generated from the lower digits, and it is not in the normal counting operation state. Become.

In the above embodiment, an exclusive OR gate is used as the first control circuit, a Nants gate is used as the second control circuit, and a flip-flop is used as the delay circuit. It can also be constructed using a similar circuit.

〔Effect of the invention〕

As explained above, the present invention can easily operate the counter in a short time by simply adding, for example, a flip-flop and a Nant gate to the lowest digit and exclusive OR gates to the other digits to the count enable input of the counter. It has the effect of allowing accurate testing.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. Figure 2 is an operation timing chart. 1 to 4...Counter, 10 to 12...Exclusive OR gate, 20...Flip-flop, 21...Nando game-1, 50...Clock signal, 60...Test mode setting signal, 7o...Reset signal, 80-84.
...Carry signal. 1 Horned Heron Example Leather 1 Diagram

Claims (1)

[Claims] (1) In a counter circuit configured by cascading a plurality of multi-bit counters (1 to 4), each counter (1 to 4) except the lowest digit counter (4) of the above counter circuit
3) is connected to a first control circuit (10 to 12) that controls the counting operation by a test mode setting signal (60) and a carry signal (81 to 83) from the lower digit counter, and the above counter circuit The lowest digit counter (4) has a delay circuit (20) that delays the carry signal output from its own counter by one clock, and the carry signal (84) delayed by one clock and the test mode setting signal. A counter circuit characterized in that it is connected to a second control circuit (21) that controls a counting operation.