JPS6384316A - Logic circuit for cmos gate array - Google Patents

Abstract

PURPOSE:To easily form a floating preventing circuit when many bases are used by using a high impedance circuit as a pull-up resistance. CONSTITUTION:In a normal transfer mode the output circuit of a circuit 10 or 20 is set under an active or floating state by the enable control input 4 for transfer of data. However a bus line 8 is set mistakenly under a floating state if both circuits 10 and 20 are not active. In this respect, a VDD is connected to the line 8 with a high impedance pull-up P-FET 30 kept always in an ON state. The FET 30 is set at an impedance much higher than the ON resistance of other internal transistors. Thus the normal transfer mode is not affected. In such a way, a floating preventing circuit is easily obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the function of gate arrays, and in particular to a method of using high ON resistance transistors as pull-up resistors.

[Conventional technology]

Conventionally, a method for preventing bus signal lines from floating has been to create a combination of logic circuits. For example, as shown in FIG. 2, the floating prevention logic circuit 40 inputs the tristate control signal 4 of each bus driver receiver 1.0.20 and inputs the negation of the logical sum thereof as the enable signal of the tristate inverter bus.

Here, the tri-state signal is active at logic "1#" and non-active, ie, floating, at logic "V"0.

In the figure, 1 is the tri-state output circuit (driver), 2 is the output of the tri-state output circuit 1, 3 is the input,
4 is an enable control input of the tri-state output circuit 1; 5 is an input circuit (receiver), 6 is an output of input circuit 5, 7 is an input, 8 is a pass line, 41 is a NOR circuit, 4
2 is a tri-stay 1-inverter.

[Problem that the invention seeks to solve]

In the conventional method described above, in the case of a logic structure requiring many internal path lines, it was necessary to add logic to prevent the signal lines from floating. When the signal line becomes floating, the P-channel transistor and N-channel transistor of 0MO8 become OFF at the same time.
This is because in the case of NL, a large communication current may flow or malfunction may occur.

In the conventional method, it is necessary to route as many wires as the number of bus driver receivers connected to one pass line and perform logical operations on them. There was a drawback that wiring channels were used.

An object of the present invention is to provide a logic circuit that can easily constitute a floating prevention circuit when a large number of buses are used.

[Means for solving problems]

The present invention relates to a CMOS gate array logic circuit in which cells of the same shape are repeatedly arranged in an array, in which a cell including a transistor having high impedance is built into a part of the internal cells. It is.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, 1 is a tri-state output circuit, 5 is an input circuit, and the output 2 of the output circuit 1 and the input cuff of the input circuit 5 are connected, and these are connected to a pass line 8. Although the input 3 of the output circuit 1 and the output 6 of the input circuit 5 are connected to separate circuits, they are omitted here. These two input/output circuits 1 and 5 are shown at 10.20. In the normal transfer mode, the output circuit of either the circuit 10 or 20 is made active or floating by the enable control manual 4 to transfer data. However, circuit 10
and 20 are not active, pass line 8
becomes floating, so the high impedance pull-up P-channel transistor 30 is always turned on.
Connect it to vDD and pass line 8 while leaving it as . Since this P-channel transistor 30 is set to have a sufficiently higher impedance than the ON resistance of other internal transistors, it does not affect the normal transfer mode.

However, when the pass line 8 begins to float, it changes to the VOO value.

〔Effect of the invention〕

As explained above, the present invention has the advantage that by using a high impedance circuit, for example, as a pull-up resistor, it is possible to easily configure a floating prevention circuit when a large number of buses are used.

Conventionally, as the number of circuits connected to a bus increases, the number of floating prevention circuits increases, and a large number of route channels are used to connect them.However, according to the present invention, one circuit is used for the pass line. This has the effect of improving gate density.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional example. 1... Tri-state output circuit (driver), 5.
...Input circuit (receiver), 8...Pass line, 3
0...High impedance pull-up P channel transistor

Claims (1)

[Claims] (1) C in which cells of the same shape are repeatedly arranged in an array
A CMOS gate array logic circuit characterized in that a cell including a transistor having high impedance is built into some of the internal cells in the logic circuit for a MOS gate array.