JPS6383972A - Detecting circuit for pll data area of digital reproducing device - Google Patents

Abstract

PURPOSE:To accurately detect a PLL data area by counting the number of times of coincidence between a pulse signal generated at a period corresponding to frequency division data and a window pulse which is generated when a prescribed number of reference clocks are counted. CONSTITUTION:Digitized data DATAP has the frequency divided by a 1/n frequency dividing circuit 71 to generate not only the pulse signal from an edge detecting circuit 72 but also a window pulse W from a monostable multivibrator circuit 78. When the pulse signal and the window pulse signal W coincide with each other, a pulse signal in the high level is generated from the output terminal of an AND circuit 76, and a counter 80 is counted up. When the counted value reaches a prescribed value, the PLL data area is detected. Thus, all PLL data areas existing in one block are accurately detected and the stable reproducing operation is effectively performed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a digital playback device such as a rotary head type digital audio recorder, and in particular to a digital playback device such as a rotary head type digital audio recorder. The present invention relates to an improvement in a PLL data area detection circuit for detecting a PLL data area when reproducing a recording medium on which digitized data including data is recorded.

(Prior Art) As is well known, in the field of audio equipment, information signals such as audio signals are digitized using PCM (pulse code modulation) technology in order to record and reproduce as high density and high fidelity as possible. BACKGROUND ART Digital recording and reproducing systems that convert the converted data into digital data, record it on a recording medium, and reproduce it are becoming popular.

Among these, those that use magnetic tape as a recording medium are called digital audio chip recorders.
For example, there are fixed head types with multiple heads arranged in the width direction of the tape, and helical scans in which the tape is wound around a cylindrical drum with heads that rotate along the circumference. There is also a rotating head type.

Here, FIG. 4 shows the overall configuration of the rotary head type digital audio chip recorder. That is, reference numeral 11.12 in the figure denotes a pair of reel stands, each of which is driven by a reel motor 13.14 to rotate in the counterclockwise direction in the figure, so that the tape 15 is run in the direction indicated by arrow a in the figure. is being done.

Furthermore, a cylindrical drum 1G, a capstan 17, and a pinch roller (not shown) are arranged between the pair of reel stands 11 and 12.

Among these, the drum 16 has a pair of recording/reproducing heads (hereinafter referred to as heads) facing outward from each other with the center of rotation of the drum 16 in between.
ia, 19 is supported. Also, this drum 1
6 is adapted to be rotated counterclockwise in the figure by a drum motor 20.

During recording and reproduction, the tape 15 is placed on the drum 16 within an opening angle range of 90° from the center of the drum 16, as shown in the figure.
It is wound diagonally around the circumferential side of 6 with a certain inclination. Further, the capstan 17 is connected to a capstan motor 21.
The pinch roller is rotated counterclockwise in the figure at a constant speed, and the pinch roller is pressed against the tape 15, so that the tape 15 is run at a constant speed. Therefore, on the tape 15, tracks corresponding to the head 18 and tracks corresponding to the head 19 are alternately formed with a constant inclination.

In this case, the head 18 is supported by the drum 16 with an azimuth angle of +20° with respect to the track forming direction, and the head 19 is supported with an azimuth angle of −2° with respect to the track forming direction.
It is supported by a drum 16 with an azimuth angle of 0.06.

Next, the recording/reproducing operation will be explained. First, during recording, digitized data DA is obtained by converting the information signal into PCM.
TAR is provided to input terminal 22 . Then, this digitized data DATAR is added with various control data D, which will be described later, by the recording signal generation circuit 23, and then sent to the switch circuit 25, which is switched and controlled by the recording head clock signal HDCKR output from the clock generation circuit 24. and the head 18 . via gate circuits 26 , 27 .
19.

Here, the clock generation circuit 24 generates the recording clock signal HDCKR and other clock signals to be described later based on a system clock signal SC of a constant frequency generated by, for example, a crystal, which is supplied to an input terminal 28. etc.

The switch circuit 25 also includes a clock generation circuit 24.
Based on the recording head clock signal HDCKR output from the recording head clock signal HDCKR, the output data of the recording signal generation circuit 23 is switched to be guided to the head 18 while the head 18 is in contact with the tape 15, and the head 19 is guided to the tape 15. During the period of contact, the output data of the recording signal generation circuit 23 is switched to be guided to the head 19.

Furthermore, the gate circuits 26 and 27 are in a state in which an H level signal is supplied to the input terminal 29, which is supplied with an H level signal in the recording mode and an L level signal in the playback mode (i.e. In recording mode), the gate is opened and the output data of the recording signal generation circuit 23 is supplied to the heads 18 and 19.

Therefore, in the recording mode, the digitized data DATAR supplied to the input terminal 22 is alternately supplied to the heads 18 and 19, and the digitized data DATAR is recorded onto the tape 15 here. be.

Furthermore, during reproduction, the reproduced signals RF obtained from each head 18 and 19 are taken out via capacitors C1 and C2, amplifiers 30 and 31, equalizer circuits 32 and 33, and switch circuit 34, respectively, and are supplied to data slice circuit 35. be done. This switch circuit 34 is connected to a rad floater signal H for reproduction outputted from the clock generation circuit 24.
Switching is controlled based on DCKP.

That is, the switch circuit 34 is switched to guide the reproduction signal RF of the head 18 to the data slice circuit 35 during the period when the head 18 is in contact with the tape 15 by the reproduction RAD clock signal HDCKP,
During the period when the head 19 is in contact with the tape 15, the reproduction signal RF of the head 19 is switched to be guided to the data slice circuit 35. For this reason, the data slice circuit 35
The reproduced signals RF obtained from each head 18 and 19 are alternately supplied to the heads 18 and 19.

Here, the data slice circuit 35 waveform-shapes the input reproduction signal RF and converts it into digitized data DATAP.
is generated. The generated digitized data DATAP is supplied to a PLL (phase locked loop) circuit 36 and used to generate a data extraction clock signal PLCK.

This data extraction clock signal PLCK is
It is supplied to the synchronization signal protection circuit 37 together with the digitized data DATAP to generate a synchronization signal SYMC. The synchronization signal 5YNC is timing-adjusted by the timing control circuit 38 and then supplied to three 10-bit to 8-bit conversion circuits together with the digitized data DATAP.

This 10-8 conversion circuit 39 separates the input digitized data DATAP into an information signal component and the control data D component, outputs the information signal component to the error correction circuit 40, and outputs the control data D component. It is output to the address generation circuit 41. The information signal supplied to the error correction circuit 40 is subjected to predetermined error correction processing, and then
It is converted into an analog signal by a D/A (digital/analog) conversion circuit 42, and is supplied to an analog playback circuit system (not shown) via an output terminal 43, where the tape 1 is output.
The data recorded in 5 is played back.

On the other hand, the address generation circuit 41 extracts an address data component from the input control data D, and outputs it to the output terminal 4.
4 to, for example, a circuit (not shown) that performs a data search operation.

Next, the drum motor 20 is controlled by a drum servo circuit described below so that its rotational speed remains constant during recording and reproduction. That is, the drum 1
A head 45 for frequency detection and a head 46 for position detection are installed near 6. Among these, the head 45 is a rotating body (
(not shown), which is installed opposite the drum 1
The frequency signal DFG corresponding to the rotation speed of 6 is generated. The frequency signal DFG obtained from the head 45 is transmitted to the drum servo circuit 4 via an amplifier 47.
8.

On the other hand, the heads 46 are installed facing a rotating body (not shown) that rotates together with the drum 16 and has a magnetization pattern for position detection formed thereon, and each head 18. A position signal DPG is generated as a reference for determining the position of 19. and,
The position signal DPG obtained from the head 46 is supplied to the drum servo circuit 48 via an amplifier 49 and a delay circuit 50.

Here, the drum servo circuit 48 includes each head 45,
Frequency signal DFG and position signal DPG obtained from 46
and the drum servo reference clock signal GK generated by the clock generation circuit 24 are compared in frequency and phase, and voltage signals corresponding to the frequency and phase differences are added and applied to the drum motor 20. supply. For this reason, the drum motor 20 is controlled to have a constant rotational speed, and the rotational speed of the drum 18 is controlled to be constant (100/3)1z).

Next, the rotational speed of the capstan motor 21 is controlled by a capstan servo circuit described below. That is, a frequency detection head 51 is installed near the capstan 17. This head 51 is installed facing a rotating body (not shown) that is rotated together with the capstan 17 and has an AC magnetization pattern (FG pattern) for frequency detection formed thereon. Frequency signal CF corresponding to
It generates G.

Then, the frequency signal CFG obtained from the head 51 is
is connected to the capstan servo circuit 53 via the amplifier 52.
is supplied to In this case, during recording, the switch circuit 5
4 is in a switching state opposite to that shown in the figure, and the reference signal K for the capstan servo generated by the clock generation circuit 24 is the frequency signal CFG obtained from the head 51.
The signal is superimposed on the signal and supplied to the capstan servo circuit 53.

The capstan servo circuit 53 compares the frequencies of the frequency signal CFG and the superimposed signal on the reference signal with the capstan servo reference clock signal GK generated by the clock generation circuit 24, and calculates the frequency difference between the two. At the same time, a voltage signal corresponding to the phase difference is generated by comparing the phases of the signal obtained by dividing the frequency of the superimposed signal and the reference clock signal GK, and a voltage signal corresponding to the phase difference is generated, and these two voltage signals are added. , which is output to the capstan motor 21.

Therefore, the capstan motor 21 is controlled to have a constant rotational speed based on the reference clock signal CK1 output from the clock generation circuit 24, and the rotational speed of the capstan 17 is constant in the recording mode. The running speed of the tape 15 is constant (8,150 II 1 m/
s).

Further, during reproduction, the switch circuit 54 is controlled to the switching state shown in the figure, and the tracking error signal TE output from the ATF circuit 55, which will be described later, is transmitted to the head 5.
The frequency signal CFG obtained from 1 is superimposed on the frequency signal CFG and is supplied to the capstan servo circuit 53. Therefore, the capstan servo circuit 51 receives the frequency signal CF.
A superimposed signal of G and tracking error signal TE, and a reference clock signal CK output from the clock generation circuit 24.
and generates a voltage signal according to the frequency difference, and also handles the tracking error signal TE from the superimposed signal and generates the tracking error signal TE.
and the reference clock signal OK, a voltage signal corresponding to the phase difference is generated, these two voltage signals are added together, and the result is output to the capstan motor 21.

Therefore, the capstan motor 20 is rotated at a constant speed, and the rotational speed of the capstan 17, that is, the running speed of the tape 15, is controlled to be constant in the playback mode.

Here, the ATF circuit 55 operates on each head 18.1 guided by the switch circuit 34, although the detailed operation will be described later.
Using the ATF data for tracking servo of the control data D included in the reproduced signal @RF from 9, each head 18 and 19 and the corresponding tape 15
A tracking error signal TE corresponding to a tracking deviation with respect to a track formed above is generated.

Therefore, in the playback state, the capstan motor 2
1, the rotational speed is controlled based on the tracking error signal TE, and the running speed of the tape 15 is controlled, thereby eliminating the tracking deviation and allowing each head 18, 19 to locate the center of the corresponding track. Tracking servo is performed to ensure accurate tracing.

Further, the rotational speed of the reel motors 13 and 14 is controlled by a reel servo circuit described below. That is, in a normal recording/reproduction state, the switch circuit 56 is controlled to a switching state opposite to that shown in the figure, and a tape speed detection signal output from the tape speed detection circuit 57 is supplied to the reel servo circuit 58. This tape speed detection circuit 57 receives reproduction signals RF from each head 18 and 19 obtained via the switch circuit 34.
The running speed of the tape 15 is detected by extracting periodic data components from the control data D contained therein.

Then, the reel servo circuit 58 causes each reel motor 13. A driving signal is generated, the reel stands 11 and 12 are driven to rotate at a predetermined rotational speed, and the tape 15 is supplied from the reel stand 11 and the tape 15 is wound up by the reel stand 12.

On the other hand, in a search state in which the tape 15 is run at high speed and data is read, the switch circuit 5G is controlled to the illustrated switching state. Here, heads 59 and 60 for frequency detection are installed near the reel stands 11 and 12, respectively. These heads 59 and 60 are installed facing a rotating body (not shown) that is rotated together with the reel stand 11 and 12 and on which an AC magnetization pattern (FG pattern) for frequency detection is formed. 11.1
A frequency signal RFG corresponding to the rotation speed of 2 is generated respectively.

The frequency signals RFG obtained from each of the heads 59 and 60 are supplied to the reel servo circuit 58 via amplifiers 61 and 62 and switch circuits 56, respectively.

Then, the reel servo circuit 58 controls each head 59.60.
Based on the frequency signal RFG obtained from the tape 15
The running speed is calculated, and the rotational speed of the reel motor 13, 14 is controlled based on the reel servo reference clock signal CK output from the clock generation circuit 24, so that the tape 15 is run at a constant speed. It is controlled as follows.

Here, the running speed of the tape 15 in the search state is:
A speed at which the heads 18 and 19 can stably read data is set in advance, and the speed is controlled to the set speed.

Next, FIG. 5 shows the format of tracks formed on the tape 15. In other words, one track consists of 196 blocks, with 12 blocks in the center.
Eight blocks serve as a data area in which digitized data converted into PCM is stored. Further, the control data D is recorded on both sides of this data area.

Here, the control data D is 11 from the left side in FIG.
Block margin data MARGIN.

2 blocks of PLL data, 8 blocks of subcode data, 5UB1.1 block of postamble data PA
, 3 blocks of IBG data, 5 blocks of ATF data, 3 blocks of IBG data, and 2 blocks of PLL
Data is recorded in order.

The control data D includes, from the right side in FIG. 5, 11 blocks of margin data MARGIN, 11 blocks of postamble data PA, 8 blocks of subcode data 5UB, 2 blocks of PLL data, 3 blocks of IBG data, and 5 blocks of IBG data. 3 blocks of ATF data and 3 blocks of IBG data are recorded in this order.

In the data area, digitized data is 8-bit to 10-bit converted and NRZ (non-return-to-zero) modulated and recorded.

Further, the subcode data 5UB1.5UB2 is a position information signal indicating the song number, absolute time, etc.

Furthermore, the PLL data is the subcode data 5.
usi, 5UB2 and the information signal for generating the data extracting clock signal PLCK, Zch/2
(fch is a single wave with a data rate of 9,408 MHI). Further, the margin data MARGIN and postamble data PA are each a single wave of f ch/2, and the IBG data is a single wave of f ah/6.

Here, the above-mentioned one block has 36 blocks as shown in FIG.
It is made up of symbols. Of these, 28 in the center
The symbol is a data area in which digitized data is stored. Also, on the left side of this data area in the figure, 4
Symbol control data is recorded, and four symbols of parity data Pa are recorded on the right side of the data area in the figure.

The above one symbol consists of 8 bits,
The control data of the above four symbols is as shown in FIG.
It consists of one symbol of sync data 5YNC, two symbols of words Wl and W2, and one symbol of parity data pb. Here, word W1 is the number of channels,
Emphasis.

It shows the track pitch width, frame address, etc., and word W2 shows the block address.

Further, the ATF data is transmitted to the track corresponding to the head 18 by a synchronization (SYNC) signal 81, as shown in FIG.
(fch/18) and a pilot signal (shown in a grid pattern in the figure) P (single wave of f ah/72) are formed, and a synchronization signal 82 is sent to the track corresponding to the head 19.
(fch/12) and a pilot signal (shown in a grid pattern in the figure) P.

In FIG. 8, arrows C indicate the moving direction of the heads 18 and 19, and arrow C indicates the running direction of the tape 15.

Next, the tracking servo will be explained. This tracking servo is generally an area-divided ATF.
(Automatic Track Finding) system is adopted, and among these, a 4-track self-contained system is actually used.

That is, the second track from the top in FIG.
Consider that 9 traces. First, when the head 19 reaches the recorded portion of the synchronization signal S2, the ATF circuit 55 detects the reproduction signal R from the head 19 based on the frequency.
It is determined that F is being supplied and that it is the synchronizing signal S2.

Then, at the timing when the synchronization signal S2 is detected, the ATF circuit 55 transmits the signal to the adjacent track (1 in FIG.
The level at which the head 19 reproduces the pilot signal P leaking from the top track is detected. Next, the ATF circuit 55 detects the pilot signal P leaking from the adjacent track (the third track from the top in FIG. 8) by the head 19 at a timing when a predetermined period of time has elapsed since the synchronization signal S2 was detected. Detect the level played. and,
The ATF circuit 55 calculates the difference in the level of leakage between the detected pilot signals, and calculates a tracking value corresponding to whether the head 19 is biased from the center of the track to be traced to an adjacent track on the muddy side. An error signal TE is generated.

Thereafter, the capstan motor 21 is controlled as described above based on the tracking error signal TE generated as described above, and the running speed of the tape 15 is increased to 1alJ.
Tracking servo is applied by being set to Ill.

Next, the reproduction head crotter signal) (DCKP),
The relationship with the reproduction signal RF obtained from the heads 18 and 19 will be explained. That is, FIG. 9(a) shows the reproduction RAD clock signal HDCKP, and during the period when this signal is at H level, the switch circuit 34 controls the reproduction signal obtained from the head 18, as shown in FIG. 9(b). The switch circuit 34 is switched to guide the signal RFa to the data slice circuit 35, and during the L level period, the switch circuit 34 is switched to guide the reproduced signal RFb obtained from the head 19 to the data slice circuit 35.

Then, the RAD clock signal for reproduction) - 1DcKP's 1
The cycle corresponds to one rotation of the drum 16, and the reproduction signals RFa and RFb from each head 18° 19 are obtained approximately at the center of the H level and L level periods of the reproduction RAD clock signal HDCKP. It is done like this.

Here, the reproduction signal RFa from each head 18 and 19.

A pair of RFb's constitute one frame, and the frame address of word W1 mentioned above indicates the position of this frame. Therefore, when the drum 1G rotates once, the frame addresses of all the words W1 included in the reproduced signals RFa and RFb obtained from the heads 18 and 19 have the same value.

Note that the recording clock signal HDCKR also outputs digitized data to the head 18 during its H level period.
The switch circuit 25 is switched to supply the digitized data to the head 19 during the L level period. The relationship between the recording clock signal HDCKR and the digitized data supplied to the heads 18 and 19 is substantially the same as described above.

By the way, in the digital recording and reproducing system as described above, the digitized data DATAP output from the data slice circuit 35 is divided into data area components and control data D.
The error correction circuit 40 separates the data area components into
In order to lead to this, it is necessary to generate the data extraction clock signal PLCK by the PLL circuit 36. In this case, the PLL circuit 36 detects that the digitized data DATAP sequentially output from the data slice circuit 35 has reached the PLL data area, and then
Data extraction clock signal PLCK from PLL data
I am trying to generate .

Here, FIG. 10 shows a conventional PLL circuit for detecting that the digitized data DATAP sequentially output from the data slice circuit 35 has reached the PLL data area.
It shows a data area detection circuit. That is, the reproduced signal RF supplied to the input terminal 63 is supplied to the reset input terminal R of a set-reset flip-flop circuit (hereinafter referred to as 5-RFP circuit) 64 via the data slice circuit 35.

The set input terminal S of this S-RF P circuit 64 receives the reproduction RAD clock signal HDC supplied to the input terminal 65.
KP is supplied via an edge detection circuit 66.

The output terminal Q of this 5-RFF circuit 64 is connected to the edge detection circuit 61. It is connected via a monostable multivibrator circuit 68 and an output terminal 69 to a circuit (not shown) for generating a data extraction clock signal PLCK from PLL data.

Now, consider a period in which the reproduction RAD clock signal HDcKP is at H level, that is, a state in which the reproduction signal RF obtained from the head 18 is being supplied to the data slice circuit 35, as shown in FIG. 11(a). As shown in FIG. 11 (1)), the reproduced signal RF has margin data MA
After RGIN, the PLL data area and the subcode data 5UBI area are supplied to the input terminal 63 in this order.

Then, the data slice circuit 35 compares the levels of the reproduced signal RF and the predetermined slice level Vs, and performs a level comparison as shown in FIG.
Generate digitized data as shown in C). On the other hand, the edge detection circuit 66 detects the rising edge of the reproducing RAD clock signal HOCKP at time t1, and generates an H level pulse at the set input terminal S of the 5-RFF circuit 64. For this reason, 5-RFF
The output terminal Q of the circuit 64 is set to H level at time t1 as shown in FIG. 11(d).

Then, when the data slice circuit 35 outputs the digitized data at time t2, the output of the 5-RFF circuit 64 is inverted to L level. Then, the edge detection circuit 6
7 detects the falling edge of the output of the 5-RFF circuit 64 and drives the monostable multivibrator circuit 68. Therefore, from the monostable multivibrator circuit 68,
As shown in FIG. 11(e), a pulse signal that is at H level for a period lT1 is generated, and this pulse signal is used as a detection signal for the PLL data area.

However, the following problem occurs with the conventional PLL data area detection means as described above.

First, the edge detection circuit 66 detects the rising edge of the reproduction RAD clock signal HDCKP, and the 5-RFF
The output of the circuit 64 is kept at H level, and the edge detection circuit 67 detects that the output of the 5-RFF circuit 64 is inverted to L level due to the output of the data slice circuit 35.
Since the monostable multi-bi break circuit 68 is driven, only the first PLL data area obtained among the three PLL data areas in one block is detected, as shown in FIG. This will have an adverse effect on the generation of the data extraction clock signal PLCK and, ultimately, on the final reproduction of the audio signal.

(Problems to be Solved by the Invention) As described above, the conventional PLL data area detection means cannot perform sufficient detection, which has a negative effect on stable playback operation. .

Therefore, this invention was made in consideration of the above circumstances, and it is possible to detect the PLL data area with sufficient accuracy.
Another object of the present invention is to provide an extremely good PLL data area detection circuit for a digital playback device that can effectively perform stable playback operations.

[Structure of the Invention] (Means for Solving the Problems) That is, the PLL data area detection circuit of the digital playback device according to the present invention focuses on the fact that PLL data has a single frequency, and detects sliced digital data. frequency-divided data to generate a pulse signal of a predetermined width with a period corresponding to the period of the divided data, and this pulse signal and a wind pulse signal generated by counting a reference clock signal a predetermined number of times. The number of matches is counted, and when this count value reaches a predetermined value, it is detected that the area is a PLL data area.

(Function) According to the above configuration, it is possible to detect the PLL data area without using the RAD clock signal HDCKP for reproduction, so that all the PLL data areas included in one block can be detected. can be detected, P
This makes it possible to detect the LL data area with sufficient accuracy and, in turn, to perform stable and effective reproduction operations.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In FIG. 1, 70 indicates digitized data DATA output from the data slice circuit 35.
P is the input terminal to which it is supplied. The digitized data DATAP supplied to this input terminal 70 is supplied to an edge detection circuit 72 via a 1/n frequency dividing circuit 71. This edge detection circuit 72 detects the rising edge of the frequency-divided data outputted from the 1/n frequency dividing circuit 71 in synchronization with the rising edge of the system clock signal SC supplied to the input terminal 73, and It generates a pulse signal.

The output signal of the edge detection circuit 72 is supplied to the clear input terminal CL of the counter 74 and to one input terminal of each of the AND circuits 75 and 76. This counter 74 is a 4-bit hexadecimal counter from 0 to 15.
The above input terminal 73 performs a cyclic counting operation up to
It counts the falling edges of the system clock signal SC supplied to the latch circuit 77, and generates a pulse signal to the latch circuit 77 when the count value reaches a predetermined value m.

Here, the latch circuit 77 latches the pulse signal generated from the counter 74 at the rising edge of the system clock signal SC, and generates a pulse signal to the monostable multivibrator circuit 78. This monostable multivibrator circuit 78 operates, for example, at 3 of the system clock signal SC in a state where the pulse signal is output from the latch circuit 77.
A wind pulse signal W having a width corresponding to the period is generated.

The wind pulse signal W generated from the monostable multivibrator circuit 78 is supplied to the other input terminal of the AND circuit 75 via the NOT circuit 19, and is also supplied to the other input terminal of the AND circuit 76. Supplied. Here, the output of the AND circuit 75 is supplied to the clear input terminal OL of the counter 80, and the output of the AND circuit 76 is supplied to the clock input terminal CK of the counter 8o. The counter 80 generates a pulse signal of a predetermined width when the count value reaches a preset setting (Ip). The PLL data is supplied to a circuit (not shown) for generating a data extraction clock signal PLCK.

The operation of the above configuration will be described below with reference to the timing diagram shown in FIG.

That is, the PLL data area is reached at time t11 in FIG. 2<a), and thereafter, the reproduced signal R as shown in FIG.
If F is obtained, the digitized data DATAP output from the data slice circuit 35 will be as shown in FIG. Note that the portion marked with an X in FIG. 2(C) is the portion where an error has occurred.

Then, the digital force data DATA shown in FIG. 2(C)
P is divided by the 1/n frequency divider circuit 71, details of which will be described later, and the edge detection circuit 72 generates a pulse signal as shown in FIG. 2(d), and the monostable multivibrator circuit Assume that a wind pulse signal W as shown in FIG. 7(e) is generated from 78.

Then, when the pulse signal output from the edge detection circuit 72 and the wind pulse signal W output from the monostable multivibrator circuit 78 match, the AND circuit 7
An H level pulse signal is generated from the output terminal of 6, and the counter 80 starts counting. Furthermore, if the pulse signal output from the edge detection circuit 72 and the wind pulse signal W output from the monostable multivibrator circuit 78 do not match, the pulse signal output from the output terminal of the AND circuit 75 as shown in FIG. A high-level pulse signal is generated at the appropriate timing, and the counter 80 is cleared. Therefore, the count value of the counter 80 is as shown in Fig. 2 (g).
The changes will be made as shown below. Here, if the set value p set in the counter 80 is 4, the count value has become 4, that is, the pulse signal output from the edge detection circuit 72 and the window output from the monostable multivibrator circuit 78. At time t12 when the pulse signal W coincides with the pulse signal W four times in succession, the counter 80 generates an H-level pulse signal as shown in FIG. This is used as the detection signal.

Here, FIG. 3 shows the timing of each part by expanding the range of period Tll in FIG. 2. That is, if frequency-divided data as shown in FIG. 3(a) is output from the 1/n frequency divider circuit 71, and a system clock signal SC as shown in FIG. 3(b) is supplied to the input terminal 73. do. Then, the edge detection circuit 72 detects the rising edge of the frequency-divided data, and generates a pulse signal with a width of one period of the system clock signal at the rising edge of the system clock signal SC, as shown in FIG. 3(C). Occur.

At this time, the counter 74 is cleared in synchronization with the fall of the pulse signal output from the edge detection circuit 72, as shown in FIG. 3(d), and thereafter is cleared in synchronization with the fall of the system clock signal SC. Then, an up-count operation will be performed. In this case, since FIG. 3 shows a normal operating state, the timing at which the pulse signal output from the edge detection circuit 72 is generated is synchronized with the timing at which the count value of the counter 74 changes from 15 to O. .

Here, the aforementioned predetermined value m set in the counter 74 is 1
4, the counter 74 generates an H level pulse signal when the count value reaches 14, as shown in FIG. 3(e). Then, based on this pulse signal, from the monostable multivibrator circuit 78,
As shown in Figure 3(f), 3 of the system clock signal
A wind pulse signal W having a width corresponding to the period is generated.

In this case, since the pulse signal output from the edge detection circuit 72 and the wind pulse signal W output from the monostable multivibrator circuit 78 match, the counter 80 is As shown, it is counted up.

Therefore, according to the configuration of the above embodiment, the PLL
Focusing on the fact that the data has a single frequency, the data sliced digitized data is frequency-divided to generate a pulse signal with a predetermined width at a period corresponding to the frequency-divided data period, and this pulse signal and The system clock signal SC is counted a predetermined number of times, and the number of times that the generated wind pulse signal W matches is counted, and when this count value reaches a predetermined value, it is detected that the PLL data area is present. , all the PLL data existing in one block can be detected accurately, and as a result stable playback operation can be performed effectively.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the invention] Therefore, as detailed above, according to this invention, P
It is possible to provide an extremely good PLL data area detection circuit for a digital playback device that can detect the LL data area with sufficient accuracy and effectively perform stable playback operations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a PLL data area detection circuit of a digital playback device according to the present invention, and FIG.
3 and 3 are timing diagrams for explaining the operation of the same embodiment, respectively. FIG. 4 is a block configuration diagram showing a rotary head type digital audio chip recorder, and FIGS. 5 to 7 are each a one-track diagram. FIG. 8 is a diagram for explaining the format of recorded data, FIG. 8 is a diagram showing details of ATF data, FIG. 9 is a timing diagram showing the relationship between the reproduction head clock signal and the reproduction signal obtained from the head, and FIG. FIG. 10 is a block diagram showing a conventional PLL data area detection means, and FIG. 11 is a timing diagram for explaining the operation of the conventional detection means. 11, 12... Reel stand, 13.14... Reel motor, 15... Tape, 16... Drum, 17...
・Capstan, 18°19...Head, 20...
Drum motor, 21... Capstan motor, 22...
...Input terminal, 23... Recording signal generation circuit, 24...
・Clock generation circuit, 25... Switch circuit, 26° 21... Gate circuit, 28.29... Input terminal, 3
0.31...Amplifier, 32.33...Equalizer circuit, 34...Switch circuit, 35...Data slice circuit, 36...PLL circuit, 37...Synchronization signal protection circuit, 38... ...timing control circuit, 39...1
0-8 conversion circuit, 40... error correction circuit, 41...
・Address generation circuit, 42...D/A conversion circuit, 43
．． 44...Output terminal, 45.46...Head, 47
...Amplifier, 48...Drum servo circuit, 49...
・Amplifier, 50...Delay circuit, 51...Head, 5
2...Amplifier, 53...Capstan servo circuit,
54... Switch circuit, 55... ATF circuit, 56
...Switch circuit, 57...Tape speed detection circuit, 58...Reel servo circuit, 59.60...Head, 6.1.62...Amplifier, 63...Input terminal, 64... ...5-RFF circuit, 65...input terminal, 6
6, 67... Edge detection circuit, 68... Monostable multivibrator circuit, 69... Output terminal, 70...
Input terminal, 71... 1/n frequency divider circuit, 72... Edge detection circuit, 73... Input terminal, 74... Counter, 75.76... AND circuit, 77... Latch circuit , 78...monostable multivibrator circuit, 79...
- Not circuit, 80... Counter, 81... Output terminal.

Claims (1)

[Claims] data slicing means for comparing a reproduction signal read from a recording medium on which digitized data including single-frequency PLL data is recorded with a predetermined slice level and converting it into the digitized data; PLL data extraction means for detecting the PLL data area from the digitized data and extracting the PLL data;
In a digital reproducing apparatus that reproduces digitized data output from the data slicing means based on LL data, a frequency dividing means for dividing the frequency of the digitized data output from the data slicing means to lower the frequency; Pulse generating means generates a pulse signal of a predetermined width with a period corresponding to the period of data output from the frequency dividing means, and a pulse signal outputted from the pulse generating means and a reference clock signal are counted and generated by a predetermined number of times. and a counting means for counting the number of times that the wind pulse signal coincides with the PLL data area, and when the count value of the counting means reaches a predetermined value, it is detected that the area is in the PLL data area. A PLL data area detection circuit for a digital playback device featuring features.