JPH0687334B2 - Drum control circuit of helical scan tape reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention relates to a helical scan type tape reproducing apparatus such as a rotary head type digital audio tape recorder, and particularly to supporting the head. The present invention relates to an improvement of a drum control circuit that controls the rotation speed of a rotating drum.

(Prior art) As is well known, in the field of audio equipment, information signals such as audio signals are digitalized by PCM (Pulse Code Modulation) technology in order to achieve high-density and high-fidelity recording and reproduction. Converted into digitized data and recorded on a recording medium,
Digital recording / reproducing systems for reproducing this have become popular.

Among them, the one using a magnetic tape as a recording medium is called a digital audio tape recorder. For example, a fixed head type in which a plurality of heads are arranged in the width direction of the tape and a head having a circumferential side There is a rotary head type in which a tape is wound around a cylindrical drum provided so as to rotate along with to perform a helical scan.

Here, FIG. 6 shows the overall structure of the rotary head type digital audio tape recorder. That is, in the drawing, 11 and 12 are a pair of reel stands, which are rotated in the counterclockwise direction in the drawing by the reel motors 13 and 14, respectively, so that the tape 15 travels in the direction indicated by the arrow a in the drawing. Has been done.

Further, a cylindrical drum 16, a capstan 17, and a pinch roller (not shown) are arranged between the pair of reel stands 11 and 12. Of these, a pair of recording / reproducing heads (hereinafter referred to as heads) 18 and 19 are supported on the drum 16 so as to face each other with the center of rotation interposed therebetween. The drum 16 is driven to rotate counterclockwise in the figure by a drum motor 20.

Then, at the time of recording / reproducing, as shown in the drawing, the tape 15 is obliquely wound around the peripheral side surface of the drum 16 with a certain inclination in a range of an opening angle of 90 ° from the center of the drum 16. Also,
The capstan 17 is driven to rotate counterclockwise in the drawing at a constant speed by the capstan motor 21, and the pinch roller is pressed against the tape 15 so that the tape 15 runs at a constant speed. Therefore, tape 15
The tracks corresponding to the head 18 and the tracks corresponding to the head 19 are alternately formed with a constant inclination.

In this case, the head 18 is + with respect to the track forming direction.
It is supported by the drum 16 with an azimuth angle of 20 °,
The head 19 is supported by the drum 16 with an azimuth angle of −20 ° with respect to the track forming direction.

Next, the recording / reproducing operation will be described. First, at the time of recording, digitized data DATAR obtained by converting the information signal into PCM
Are supplied to the input terminal 22. Then, the digitized data DATAR is added with various control data D to be described later output from the clock generation circuit 24 by the adder circuit 23, and then, through the switch circuit 25 and the gate circuits 26 and 27, the head 18, Supplied to 19.

Here, the clock generation circuit 24 is for generating the control data D and other clock signals described later based on the system clock signal SC having a constant frequency supplied to the system clock signal input terminal 28.

The switch circuit 25 is switch-controlled based on the recording head clock signal HDCKR output from the clock generation circuit 24. That is, the switch circuit 25
Head 1 by the recording head clock signal HDCKR
8 is switched so as to lead the output data of the adder circuit 23 to the head 18 while it is in contact with the tape 15, and lead the output data of the adder circuit 23 to the head 19 while the head 19 is in contact with the tape 15. It can be switched.

Further, the gate circuits 26 and 27 are set to H during the recording mode.
In the state where the H level signal is supplied to the recording / reproducing mode input terminal 29 (that is, the recording mode) to which the level signal is supplied and the L level signal is supplied in the reproducing mode, the gate is opened and the adding circuit Output data of 23 is head 1
It will be supplied to 8,19.

Therefore, in the recording mode, the digitized data DATAR supplied to the input terminal 22 is alternately supplied to the heads 18 and 19, where the digitized data DATAR to the tape 15 is supplied.
The recording of R is done.

During reproduction, reproduction signals RF obtained from the heads 18 and 19 are extracted via the capacitors C1 and C2, the amplifiers 30 and 31, the equalizer circuits 32 and 33, and the switch circuit 34, respectively, and supplied to the data slice circuit 35. To be done. The switch circuit 34 is switch-controlled based on a reproduction head clock signal HDCKP output from a position signal detection control circuit 36 described later.

That is, the switch circuit 34 is switched by the reproduction head clock signal HDCKP so as to guide the reproduction signal RF of the head 18 to the data slicing circuit 35 while the head 18 is in contact with the tape 15, and the head 19 moves to the tape 15. Data slice circuit for reproducing signal RF of head 19 during contact
It can be switched to lead to 35. Therefore, the reproduction signals RF obtained from the heads 18 and 19 are alternately supplied to the data slice circuit 35.

Here, the data slicing circuit 35 waveform-shapes the input reproduction signal RF to generate digitized data DATAP. This generated digitized data DATAP
Is supplied to a demodulation / reproduction circuit system (not shown) via the output terminal 37. Also, the digitized data DATAP is the PLL
(Phase locked loop) supplied to the circuit 38 and the data sampling clock signal PLCK is generated. The data sampling clock signal PLCK is supplied to the demodulation / reproduction circuit system through the output terminal 39 and used for the demodulation / reproduction operation.
The data recorded on the disc is reproduced.

Next, the drum motor 20 is controlled by a drum servo circuit described below so that its rotation speed becomes constant. That is, a head 40 for frequency detection and a head 41 for position detection are installed near the drum 16. Of these, the head 40 is installed facing the rotating body (not shown) on which the alternating-current magnetization pattern (FG pattern) for frequency detection is formed by being rotated together with the drum 16, and the rotation speed of the drum 16 The frequency signal DFG corresponding to is generated.

Then, the frequency signal DFG obtained from the head 40 is
The frequency is compared with the reference clock signal AFCCK which is supplied to the automatic frequency comparison circuit (hereinafter referred to as AFC circuit) 43 through the amplifier 42 and output from the clock generation circuit 24.
The AFC circuit 43 generates a voltage signal according to the frequency difference between the frequency signal DFG and the reference clock signal AFCCK and outputs it to the adding circuit 44.

On the other hand, the head 41 is rotated together with the drum 16 and has a rotating body (not shown) on which a magnetization pattern for position detection is formed.
The position signal DPG is provided so as to face each other and serves as a reference for determining the positions of the heads 18 and 19 when the drum 16 rotates.

Then, the position signal DPG obtained from the head 41 is supplied to the position signal detection control circuit 36 via the amplifier 45. The position signal detection control circuit 36 detects the input position signal DPG and generates a phase signal MDPG. And
Phase signal MDPG obtained from the position signal detection control circuit 36
Is supplied to an automatic phase comparison circuit (hereinafter referred to as an APC circuit) 46 and is compared in phase with a reference clock signal APCCK output from the clock generation circuit 24. The APC circuit 46 generates a voltage signal according to the phase difference between the phase signal MDPG and the reference clock signal APCCK and outputs it to the adder circuit 44.

Therefore, the adder circuit 44 includes an AFC circuit 43 and an APC circuit 46.
The voltage signals respectively output from are added. And
The voltage signal output from the adder circuit 44 is supplied to the drum motor 20 via the equalizer circuit 47 and the drive circuit 48, so that the drum motor 20 is controlled to have a constant rotation speed. The rotation speed of the drum 16 is controlled to be constant (100/3 Hz).

Here, in the drum servo circuit as described above, AF
Frequency signal DFG and reference clock signal AFCC by C circuit 43
The APC circuit 46 is controlled so as to be driven with the frequency difference from K falling within a certain range.

In addition, the position signal detection control circuit 36, the switch circuit 3 based on the position signal DPG obtained from the head 41.
A reproduction head clock signal HDCKP for switching 4 is generated.

Next, the rotation speed of the capstan motor 21 is controlled by a capstan servo circuit described below. That is, a frequency detection head 49 is installed near the capstan 17. This head 49
Is installed so as to face a rotating body (not shown) that is rotated together with the capstan 17 and has an AC magnetization pattern (FG pattern) for frequency detection formed thereon, and corresponds to the rotation speed of the capstan 17. The frequency signal CFG is generated.

Then, the frequency signal CFG obtained from the head 49 is
It is supplied to the capstan servo circuit 51 via the amplifier 50. The capstan servo circuit 51 has a recording / reproducing mode input terminal 52 to which an H level signal is supplied in the recording mode and an L level signal is supplied in the reproducing mode.
H level signal is being supplied (that is, recording mode)
Then, the frequency signal CFG and the reference clock signal SCK output from the clock generation circuit 24 are frequency-compared, and a voltage signal corresponding to the frequency difference is generated, and the frequency signal CFG and the divided signal are generated. Reference clock signal S
The phase comparison is performed with CK, a voltage signal corresponding to the phase difference is generated, and both voltage signals are added and output.

The voltage signal output from the capstan servo circuit 51 is supplied to the capstan motor 21 via the equalizer circuit 53 and the drive circuit 54, so that the capstan motor 21 is controlled to have a constant rotation speed. In the recording mode, the rotational speed of the capstan 17 is constant, that is, the running speed of the tape 15 is constant (8.150 mm / s).

Further, in a state where the L level signal is supplied to the recording / reproducing mode input terminal 52 (that is, the reproducing mode), the capstan servo circuit 51 outputs the frequency signal CFG and the reference clock output from the clock generating circuit 24. The signal SCK is frequency-compared, and a voltage signal corresponding to the frequency difference is generated, and the tracking error signal TE output from the ATF circuit 55 described later and the reference clock signal SCK are phase-compared to each other to determine the phase difference. Generate a corresponding voltage signal,
These voltage signals are added and output. Then, this voltage signal is applied to the equalizer circuit 53 and the drive circuit.
It is supplied to the capstan motor 20 via 54, and the rotational speed of the capstan 17, that is, the running speed of the tape 15 is controlled here in the reproduction mode.

Here, the ATF circuit 55, the reproduction signal RF from each head 18, 19 led by the switch circuit 34, the reproduction head clock signal HDCKP output from the position signal detection control circuit 36, The digitized data DATAP output from the data slice circuit 35 is supplied. Then, this ATF circuit 55 uses a reproduction head clock signal HDCKP and digitized data DATAP in the reproduction state of the tape 15 and uses the ATF signal contained in the reproduction signal RF, the detailed operation of which will be described later. , A tracking error signal TE corresponding to a tracking deviation between each head 18 and 19 and each track formed on the tape 15 corresponding thereto is generated.

Therefore, in the playback state, the capstan motor 21
The rotational speed is controlled based on the tracking error signal TE to control the running speed of the tape 15, and the tracking deviation is eliminated in each head.
Tracking servo is performed to accurately trace the center of the track corresponding to 18, 19.

Further, the reel motors 13 and 14 have reel motor control signals RMS1 and RMS2 output from the clock generation circuit 24.
However, by being respectively supplied through the drive circuits 56 and 57, they are rotationally driven at a predetermined rotation speed, and the tape 15 is supplied from the reel stand 11 and the tape 15 is wound up by the reel stand 12. .

Next, FIG. 7 shows a format of tracks formed on the tape 15. That is, one track is composed of 196 blocks, and 128 blocks in the central part are a data area for storing digitized data in PCM. Also, on both sides of this data area,
The control data D is recorded.

Here, the control data D is, from the left side in FIG. 7, margin data MARGIN of 11 blocks, PLL data of 2 blocks, subcode data SUB1 of 8 blocks, postamble data PA of 1 block, IBG data of 3 blocks. 5,
The blocks are recorded in the order of ATF data, 3 blocks of IBG data, and 2 blocks of PLL data.

Further, the control data D are, from the right side in FIG. 7, margin data MARGIN of 11 blocks, postamble data PA of 1 block, subcode data SUB2 of 2 blocks, 2
Blocks of PLL data, 3 blocks of IBG data, 5 blocks of ATF data, and 3 blocks of IBG data are recorded in this order.

In the data area, digitized data is recorded after being subjected to 8-bit-10-bit conversion and NRZ (non-return to zero) modulation. Further, the subcode data SUB1 and SUB2 are information signals indicating a music number, an absolute time and the like. Further, the PLL data includes the subcode data SUB1 and SUB2 and the data sampling clock signal PLCK.
Is an information signal for generating, and is a single wave of fch / 2 (fch is a data rate of 9.408 MHz). The margin data MARGIN and the postamble data PA are fch / 2, and the IBG data is a single wave of fch / 6.

Here, the one block is composed of 36 symbols as shown in FIG. Of these, 28 symbols in the center are the data area for storing digitized data. Control data of 4 symbols is recorded on the left side of the data area in the figure, and parity data Pa of 4 symbols is recorded on the right side of the data area in the figure.

And, the above 1 symbol is composed of 8 bits,
The control data of the above 4 symbols is as shown in FIG.
Sync data SYNC of 1 symbol, word W1, W of 2 symbols
The parity data Pb consists of 2 and 1 symbols. Here, the word W1 indicates the number of channels, emphasis, track pitch width, etc., and the word W2 indicates the block address.

In addition, the ATF data, as shown in FIG.
Sync signal S1 (fch / 18) to the track corresponding to 8
And a pilot signal (indicated by a lattice in the figure) P (single wave of fch / 72) are formed, and a synchronization signal S2 (fch / 12) and a pilot signal (lattice in the figure) are formed on the track corresponding to the head 19. And (shown in the shape) P are formed.

In FIG. 10, the arrow b indicates the moving direction of the heads 18 and 19, and the arrow c indicates the running direction of the tape 15.

Next, the tracking servo will be described. The tracking servo generally adopts an area division type ATF (Automatic Track Finding) method, and among them, the 4-track complete type is actually used.

That is, the second track from the top in FIG.
Think about tracing. First, when the head 19 reaches the recording portion of the synchronization signal S2, the ATF circuit 55 causes the reproduction signal from the head 19 to be reproduced based on the reproduction head clock signal HDCKP output from the position signal detection control circuit 36. Digitized data DA output from the data slicing circuit 35 as well as determining that RF is being supplied.
The sync signal S2 is detected based on TAP.

Then, the ATF circuit 55 detects the level at which the head 19 reproduces the pilot signal P leaking from the adjacent track (the first track in FIG. 10) at the timing when the synchronization signal S2 is detected. Next, the ATF circuit 55 causes the head 19 to output the pilot signal P leaked from the adjacent track (the third track from the top in FIG. 10) at a timing when a predetermined time has elapsed from the time when the synchronization signal S2 was detected. Detect the level played. Then, the ATF circuit 55 calculates the level difference between the detected leaks of both pilot signals,
Here, a tracking error signal TE corresponding to which side of the tracks the head 19 deviates from the center of the track to be traced by the head 19 is generated.

After that, based on the tracking error signal TE generated as described above, the capstan motor 21 is controlled as described above, the traveling speed of the tape 15 is controlled, and tracking servo is performed. is there.

Next, the reproduction head clock signal HDCKP and the head 1
The relationship with the reproduction signal RF obtained from 8, 19 will be described. That is, FIG. 11 (a) shows the reproducing head clock signal HDCKP, and during the period when this signal is at the H level, as shown in FIG. 11 (b), the reproducing signal obtained by the switch circuit 34 from the head 18 is shown. RFa is switched so as to be guided to the data slice circuit 35, and the switch circuit is operated during the L level period.
34 is switched so as to guide the reproduction signal RFb obtained from the head 19 to the data slice circuit 35.

Then, one cycle of the reproduction head clock signal HDCKP is
It corresponds to one rotation of the drum 16, and the reproduction signals RFa and RFb from the heads 18 and 19 are obtained at approximately the center of the H level and L level periods of the reproduction head clock signal HDCKP. There is.

The recording head clock signal HDCKR is also
In the level period, the switch circuit 25 is switched so as to supply the digitized data to the head 18, and the L
The switch circuit 25 is switched so as to supply the digitized data to the head 19 during the level period. Then, the recording head clock signal HDCK
The relationship between R and the digitized data supplied to the heads 18 and 19 is substantially the same as above.

(Problems to be Solved by the Invention) By the way, the digital audio tape recorder as described above is still in the stage of development, and in particular, it has a large number of parts and tends to be complicated in structure and large in size. It has the problem of being at a disadvantage.

Therefore, the present invention has been made in consideration of the above circumstances, and it is possible to reduce the number of parts and simplify the structure, and to provide an extremely good helical scan type tape reproducing apparatus capable of stably and accurately rotating and driving the drum. It is an object to provide a drum control circuit.

[Structure of the Invention] (Means for Solving the Problems) That is, the drum control circuit of the helical scan tape reproducing apparatus according to the present invention first forcibly drives the drum in a state where the rotation of the drum is required. Then, it is detected that the pattern interval of the periodic signal that can be detected among the plurality of periodic signals recorded on each track of the tape falls within a predetermined range. Then, the periods of the plurality of periodic signals are discriminated to detect the pilot signal, which is one of the periodic signals. And
The detected pilot signal and the first reference signal are frequency-compared, and the rotation of the drum is controlled according to the difference component, and the pilot signal is compared with the pilot signal in a state where the rotation speed of the drum is converged within a predetermined range. The phase is compared with the second reference signal, and the rotation of the drum is controlled according to the difference component.

(Operation) Further, according to the above configuration, since the rotation speed of the drum is controlled by using the pilot signal included in the reproduction signal obtained from the head, the rotation of the drum is detected. It is not necessary to separately provide a head or the like, and the number of parts can be reduced and the simplification of the configuration can be promoted. Further, during the rotational acceleration of the drum, it is detected that the pattern interval of the periodic signal that could be detected among the plurality of periodic signals is within a predetermined range, and then the period of the plurality of periodic signals is detected. Since the pilot signal is detected by discriminating between the two, the pilot signal can be reliably detected without being mistaken for another periodic signal, and the rotation of the drum can be controlled stably and accurately. It is a thing.

(Embodiment) Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, the same parts as those in FIG. 6 are designated by the same reference numerals, and only different parts will be described here. That is, the digitized data DATAP output from the data slice circuit 35 is supplied to the periodic pattern detection circuit 58 and the period measurement circuit 59, respectively.

Of these, the periodic pattern detection circuit 58 detects a data component having periodicity from the input digitized data DATAP to generate a detection signal C, and also corresponds to the period of the detected periodic signal. The time signal τc is generated. Here, the periodic signal is the control data D shown in FIG. 7, that is, the margin data MARGIN, PLL data, postamble data PA, IBG data and ATF data, and the same data is recorded at the same frequency. It is a signal that has been described.

Further, the period measuring circuit 59 measures the period obtained by dividing the input digitized data DATAP by 1 / n, and outputs the measured signal nτc.
Is output.

Then, the detection signal C output from the periodic pattern detection circuit 58 is supplied to the counter circuit 60. The counter circuit 60 clears the count value and performs the up-counting operation from 0 again each time the detection signal C is supplied. The counter circuit 60 measures the interval τ1 in which the periodic signal is detected by the count value. The detection signals K1 and K2 indicating that the interval τ1 is within a predetermined range are output to the clock generation circuit 24.

Further, the time signal τc output from the periodic pattern detection circuit 58 is supplied to the pilot signal detection circuit 61. The pilot signal detection circuit 61 determines the pilot signal P based on the input time signal τc and outputs it to the clock generation circuit 24, the APC circuit 46 and the latch circuit 62.

Here, the latch circuit 62 latches the measurement signal nτc output from the period measurement circuit 59 at the time when the pilot signal P is supplied, and outputs it to the AFC circuit 43.

Therefore, the measurement signal nτc and the reference clock signal AFCCK output from the clock generation circuit 24 are the AFC circuit 43.
The frequency comparison is performed by and the voltage signal corresponding to the difference component is generated. The pilot signal P and the reference clock signal APCCK output from the clock generation circuit 24 are phase-compared by the APC circuit 46, and a voltage signal corresponding to the difference component is generated.

The voltage signals output from the AFC circuit 43 and the APC circuit 46 are supplied to both input terminals of the adder circuit 44 via the gate circuits 63 and 64, respectively. These gate circuits
63 and 64 are opened and closed by the gate signals G1 and G2 output from the clock generation circuit 24, respectively.

Here, a series of operations from the state where the rotation of the drum 16 and the running of the tape 15 are stopped to the time when the reproduction of the tape 15 is requested and the drum 16 is controlled to a predetermined rotation speed (100/3 Hz) , With reference to the flow chart shown in FIG.

First, in step S1, when playback of the tape 15 is requested,
In step S2, the switch circuit 34 is fixed to a state in which only the reproduction signal RFa from the head 18 is guided to the data slice circuit 35 while the tape 15 is stopped running. At this time,
The clock generation circuit 24 generates gate signals G1 and G2 forcibly setting the outputs of the gate circuits 63 and 64 to the H level,
The drum motor 20, that is, the drum 16 is forcibly driven to rotate.

Therefore, the reproduction signal RFa output from the head 18 is converted into digitized data obtained through the data slice circuit 35.
DATAP has a periodic pattern detection circuit 58 and a period measurement circuit 5
9, will be supplied respectively. Then, in step S3, the periodic pattern detection circuit 58 detects the periodic signal and generates the detection signal C. Further, the generation interval τ1 of the detection signal C is measured by the counter circuit 60.

Then, in step S4, the counter circuit 60 determines whether or not the measured interval τ1 is in a range longer than a preset predetermined time τmin.

Here, the frequency of the periodic signal is, as shown in FIG. 3, fch / 2, fch / 6, fch / 18 (fch / 12 if the synchronizing signal S2).
There are also fch / 72 types. In this case, fch is the data rate frequency as described above, and for example, the diameter of the drum 16 is
When the wrap angle of the tape 15 is 90 ° at 30 mm, fcho = 9.40
It will be 8MHz. One block is fch / 360.

Therefore, when the rotation speed N of the drum 16 is 100/3 Hz (= No), fch is fcho, so the relationship between fch and N is fch = (fcho / No) N. That is, when the number of rotations of the drum 16 approaches from 0 to No, fch also approaches from 0 to fcho.

Here, since the reproduction signal band of the tape 15 is about 200 KHz to 5 MHz, the drum 16 starts to rotate, that is, N
≪No, all playback signals RFa from head 18 are 0
Has become. Therefore, the periodic pattern detection circuit 58,
No periodic signal of any frequency can be detected, and as a result, the determination result of step S4 is NO.

Then, in step S5, the clock generation circuit 24 continues the compulsory circuit of the drum motor 20, increases the rotation speed, returns to step S3, and is used again for the determination in step S4.

Then, when the rotation speed of the drum 16 becomes slightly higher and the fch / 2 component signal having the highest frequency among the periodic signals comes to be obtained at a frequency exceeding the minimum frequency of 200 KHz in the reproduction band, the periodic pattern The detection signal C is obtained from the detection circuit 58.

That is, as shown in FIG. 4A, if the reproduction signal RFa from the head 18 is obtained (the reproduction signal RFb from the head 19 cannot be obtained because the switch circuit 34 is fixed,
In the control data area D, the detection signal C is generated as shown in FIG. 4 (b).

In this case, since the rotation speed of the drum 16 is still low, the head 19
Since the head 18 reproduces the leakage of the control data D (particularly the pilot signal P) recorded on the track corresponding to the detection signal C, even in the control data area D of the reproduction signal RFb.
Will be able to get.

Then, as shown in FIG. 4C, the counter circuit 60 repeats the operation of clearing the count value and counting up again from 0 in synchronization with the generation timing of the detection signal C. In this case, the counter circuit 60
During the counting operation, as shown in FIG. 4 (d), an L level signal is output to the clock generation circuit 24, but it is not cleared even if the predetermined time τmin has elapsed since the detection signal C was input. That is, if the detection signal C is not obtained, H
The level detection signal K1 is now generated, and the step S4
The result of the determination in is YES.

That is, the clock generation circuit 24 can determine that the generation interval τ1 of the detection signal C has a time longer than τmin.

Next, when the rotation speed of the drum 16 is further increased, the step
In S6, the counter circuit 60 measures the detection signal C by the interval τ
It is determined whether or not 1 is in a range shorter than a predetermined time τmax set in advance. Then, the rotation speed of the drum 16 becomes faster than the above No, and the generation interval τ1 of the detection signal C becomes τ.
When it becomes shorter than max, the determination result of step S6 becomes NO.

Then, in step S7, the clock generation circuit 24 forcibly reduces the rotation speed of the drum motor 20, lowers the rotation speed of the drum 16, and returns to step S3.
Use the item 6 for discrimination.

Then, if the determination result in step S6 is YES, the counter circuit 60 causes the clock generation circuit 24 to generate the H-level detection signal K2. That is, step S
4, the generation interval τ1 of the detection signal C of the periodic signal by S6
As a result, the clock generation circuit 24 can determine that there is an object within the range between τmin and τmax. Conversely, this means that the rotational speed of the drum 16 falls within the range defined by τmin and τmax.

Here, of the reproduction signal RFa from the head 18, the portion excluding the control data D is 128 blocks, and the period in which none of the heads 18 and 19 is in contact with the tape 15 is 196 blocks. , Τmin and τmax above
It can be set to 128,196 (block length). In this case, when the rotation speed of the drum 16 falls within the range defined by τmin and τmax, the drum 16
The rotation speed of is It is possible to converge in the range of.

Next, in step S8, the pilot signal detection circuit 61 detects the pilot signal P based on the time signal τc output from the periodic pattern detection circuit 58. This detection operation is realized by detecting the longest one of the time signals τc because the longest one of the periodic signals is the pilot signal P.

Then, at the timing when the pilot signal P is output from the pilot signal detection circuit 61, the latch circuit 62 is output.
Is to latch the measurement signal nτc output from the period measuring circuit 59 and output it to the AFC circuit 43. In this case, the measurement signal nτc corresponds to the period of the pilot signal P multiplied by n.

After that, in step S9, the clock generation circuit 24 generates the gate signal G1 for opening the gate circuit 63. Therefore, the output voltage signal of the AFC circuit 43 is supplied to the drum motor 20 via the gate circuit 63, the addition circuit 44, the equalizer circuit 47, and the drive circuit 48, and the rotation speed of the drum 16 corresponds to the reference clock signal AFCCK. AFC servo is applied so that it converges to the rotation speed.

In this case, when the frequency division ratio n by the period measuring circuit 59 is 4, the measurement signal Nτc becomes 1 / (4 × 72fch), and the rotation speed of the drum 16 is ± 100 / (4 X72) = ± 0.35%.

After that, in step S10, when it is determined that the AFC servo is locked stably, in step S11, the clock generation circuit 24 causes the gate signal to open the gate circuit 64.
G2 is generated. Therefore, the output voltage signal of the APC circuit 46 is added to the voltage signal output from the AFC circuit 43 via the gate circuit 64, and the rotation speed of the drum 16 is maintained at the specified rotation speed (100/3 Hz). It will be done.

That is, after step S6, as shown in FIG. 5A, the reproduction signal RFa obtained from the head 18 and the head 1 are reproduced.
8 reproduces the leakage of the pilot signal P recorded in the track corresponding to the head 19, and FIG.
As shown in, the pilot signal P is detected, and the drum servo is performed based on this pilot signal.

Therefore, according to the configuration of the above embodiment, the tape
Since the drum servo is performed using the pilot signal P recorded in advance in 15, the heads 40, 41 and the like are not required as in the conventional case, the number of parts is reduced, and the simplification of the configuration is promoted. And can be economically advantageous.

Further, the pilot signal P is detected by detecting that the generation interval τ1 of the periodic signal is within a predetermined range, so that the pilot signal P can be surely detected. That is, during the period from the stopped state of the drum 16 until the drum 16 reaches the specified number of revolutions by being sequentially accelerated,
The frequency of the periodic signal obtained from the head 18 is
The rotation speed is low in a slow state, and becomes a normal value as the rotation speed of the drum 16 approaches the specified speed.

Therefore, for example, the frequency of the signal of the fch / 2 component of the periodic signal changes from a low frequency to a high frequency in sequence as the rotation speed of the drum 16 increases, and the drum 16 reaches a specified rotation speed. Then, you will get fch / 2. Then, in this way, the frequency of the signal of the fch / 2 component may become equal to the frequency fch / 72 of the pilot signal P in the process of changing the frequency. Therefore, if the pilot signal detection circuit 61 detects only the period of the periodic signal, the signal of the fch / 2 component may be erroneously detected as the pilot signal P.

Therefore, the rotation speed of the drum 16 is increased until the generation interval τ1 of the periodic signal falls between τmin and τmax, and the pilot signal P is generated by the period of the periodic signal obtained in this state.
Is detected, the pilot signal P can be surely detected without any error.

The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

[Effects of the Invention] Therefore, as described in detail above, according to the present invention, the number of parts can be reduced and the configuration can be simplified, and at the same time, a very good helical scan method capable of stably and accurately rotating the drum. A drum control circuit of a tape reproducing device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a drum control circuit of a helical scan type tape reproducing apparatus according to the present invention, FIG. 2 is a flow chart for explaining the operation of the embodiment, and FIG. 3 is control data. 4 and 5 are timing charts of respective parts for explaining the operation of the embodiment, and FIG. 6 is a drum control circuit of a conventional helical scan type tape reproducing apparatus. The block diagram shown in FIGS. 7 to 9 is 1
FIG. 10 is a diagram for explaining a format of data recorded on a track, FIG. 10 is a diagram showing details of ATF data, and FIG. 11 is a timing diagram showing a relation between a reproduction head clock signal and a reproduction signal obtained from the head. Is. 11,12 …… Reel stand, 13,14 …… Reel motor, 15 …… Tape, 16 …… Drum, 17 …… Capstan, 18,19 ……
Head, 20 ... drum motor, 21 ... capstan motor, 22 ... input terminal, 23 ... addition circuit, 24 ... clock generation circuit, 25 ... switch circuit, 26, 27 ... gate circuit, 28 ... … System clock signal input terminal, 29 …… Recording / playback mode input terminal, 30,31 …… Amplifier, 32,33 …… Equalizer circuit, 34 …… Switch circuit, 35 …… Data slice circuit, 36 …… Position signal detection Control circuit, 37 ... Output terminal, 38 ... PLL circuit, 39 ... Output terminal, 40, 41 ... Head, 42 ... Amplifier, 43 ... AFC circuit, 44 ... Addition circuit, 4
5 …… Amplifier, 46 …… APC circuit, 47 …… Equalizer circuit,
48 …… Drive circuit, 49 …… Head, 50 …… Amplifier, 51 ……
Capstan servo circuit, 52 …… Record / playback mode input terminal, 53 …… Equalizer circuit, 54 …… Drive circuit, 55 …… AT
F circuit, 56, 57 ... Drive circuit, 58 ... Periodic pattern detection circuit, 59 ... Period measurement circuit, 60 ... Counter circuit, 61 ...
… Pilot signal detection circuit, 62 …… Latch circuit, 63,64
...... Gate circuit.

Claims (1)

[Claims] 1. A tape in which periodic signals of different frequencies including a low-frequency pilot signal are recorded in each track, and a drum in which a head is arranged on the circumferential side with which the tape is in contact, are provided. In a drum control circuit of a helical scan type tape reproducing device for controlling the drum to be rotationally driven from a stopped state and held at a specified rotational speed, the drum is forcibly rotationally accelerated while the drum is requested to rotate. The first detecting means for detecting that the pattern interval of the periodic signals that could be detected among the plurality of periodic signals in the rotating state of the drum is within a predetermined range, and the first detecting means. Second detection means for detecting the pilot signal by discriminating the cycles of the plurality of periodic signals in a detection state; and the second detection means for detecting the pilot signal. Frequency comparison means for comparing the frequency of the ylot signal and the first reference signal and generating a control signal for controlling the rotation of the drum according to the difference component, and the rotation speed of the drum within a predetermined range by the frequency comparison means. Phase comparison for generating a control signal for controlling the rotation of the drum in accordance with the difference component of the pilot signal detected by the second detection means and the second reference signal in the state of being converged to And a drum control circuit of a helical scan type tape reproducing apparatus.