JPS6383988A - Data retrieving circuit for digital reproducing device - Google Patents

Abstract

PURPOSE:To perform a search operation as quickly as possible and to shorten the search time by increasing the driving speed of a recording medium until the error occurrence rate of data read in the search state exceeds a prescribed level. CONSTITUTION:In the search state, a detecting circuit 63 detects a number (m) of blocks, where error does not occur, out of blocks of reproduced digital data based on the error correction processing of an error correcting circuit 40. A reel servo circuit 58 is controlled to control rotative speeds of reel motors 13 and 14 according as the number (m) of blocks is larger than a prescribed value or not, thus adjusting the running speed of a tape 15. Thus, the tape speed is increased as long as data is read without the occurrence of error, and the quick search operation is realized.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a digital playback device such as a rotary head type digital audio recorder, etc. Concerning improvements to search circuits.

(Prior Art) As is well known, in the field of audio VI equipment, information signals such as audio signals are processed using PCM (Pulse Code Modulation) technology in order to achieve high-density and high-fidelity recording and playback. BACKGROUND ART Digital recording and reproducing systems that convert data into digitized data, record it on a recording medium, and reproduce it are becoming popular.

Among these, those that use magnetic tape as a recording medium are called digital audio chip recorders.
For example, there are fixed head types with multiple heads arranged in the width direction of the tape, and helical scans in which the tape is wound around a cylindrical drum with heads that rotate along the circumference. There is also a rotating head type.

Here, FIG. 3 shows the overall configuration of the rotary head type digital audio tape recorder. That is, reference numerals 11 and 12 in the figure denote a pair of reel stands, which are each rotated counterclockwise in the figure by reel motors 13 and 14, so that the tape 15 is run in the direction indicated by arrow a in the figure. being done.

Further, a cylindrical drum 16, a capstan 17, and a pinch roller (not shown) are arranged between the pair of reel stands 11 and 12.

Among these, the drum 16 has a pair of recording/reproducing heads (hereinafter referred to as heads) facing outward from each other with the center of rotation in between.
18.19 is supported. Also, this drum 16
is rotated counterclockwise in the figure by a drum motor 20.

During recording and reproduction, the tape 15 is placed on the drum 16 within an opening angle range of 90° from the center of the drum 16, as shown in the figure.
It is wound diagonally around the circumferential side of 6 with a certain inclination. Further, the capstan 17 is connected to a capstan motor 21.
The pinch roller is rotated counterclockwise in the figure at a constant speed, and the pinch roller is pressed against the tape 15, so that the tape 15 is run at a constant speed. Therefore, on the tape 15, tracks corresponding to the head 18 and tracks corresponding to the head 19 are alternately formed with a constant inclination.

In this case, the head 18 is supported by the drum 16 with an azimuth angle of +20° with respect to the track forming direction, and the head 19 is supported with an azimuth angle of −2° with respect to the track forming direction.
It is supported by the drum 16 with an azimuth angle of 0''.

Next, the recording/reproducing operation will be explained. First, during recording, digitized data DA is obtained by converting the information signal into PCM.
TAR is provided to input terminal 22 . Then, this digitized data DATAR is added with various control data D, which will be described later, by the recording signal generation circuit 23, and then sent to the switch circuit 25, which is switched and controlled by the recording head clock signal HDCKR output from the clock generation circuit 24. and the head 18 . via gate circuits 26 , 27 .
19.

Here, the clock generation circuit 24 generates the recording clock signal HDCKR and other clock signals to be described later based on a system clock signal SC of a constant frequency generated by, for example, a crystal, which is supplied to an input terminal 28. etc.

The switch circuit 25 also includes a clock generation circuit 24.
Based on the recording head clock signal HDCKR output from the recording head clock signal HDCKR, the output data of the recording signal generation circuit 23 is switched to be guided to the head 18 while the head 18 is in contact with the tape 15, and the head 19 is guided to the tape 15. During the period of contact, the output data of the recording signal generation circuit 23 is switched to be guided to the head 19.

Furthermore, the gate circuits 26 and 27 are in a state in which an H level signal is supplied to the input terminal 29, which is supplied with an H level signal in the recording mode and an L level signal in the playback mode (i.e. In recording mode), the gate is opened and the output data of the recording signal generation circuit 23 is supplied to the heads 18 and 19.

Therefore, in the recording mode, the digitized data DATAR supplied to the input terminal 22 is alternately supplied to the heads 18 and 19, and the digitized data DATAR is recorded onto the tape 15 here. be.

Furthermore, during playback, the playback signals RF obtained from each head 18 and 19 are sent to the respective capacitors CI.

C2, amplifiers 30 and 31, equalizer circuits 32 and 33, and switch circuits 34, and are supplied to a data slice circuit 35. This switch circuit 34 is switched and controlled based on the reproduction bed clock signal HDCKP output from the clock generation circuit 24.

That is, the switch circuit 34 is switched to guide the reproduction signal RF of the head 18 to the data slice circuit 35 during the period when the head 18 is in contact with the tape 15 by the reproduction RAD clock signal HDCKP,
During the period when the head 19 is in contact with the tape 15, the reproduction signal RF of the head 19 is switched to be guided to the data slice circuit 35. Therefore, the data slice circuit 35
The reproduced signals RF obtained from each head 18 and 19 are alternately supplied to the heads 18 and 19.

Here, the data slice circuit 35 waveform-shapes the input reproduction signal RF and converts it into digitized data DATAP.
is generated. This generated digitized data DATAP is sent to a PLL (phase locked loop) circuit 36.
and is used to generate a data extraction clock signal PLCK.

This data extraction clock signal PLCK is
It is supplied to the synchronization signal protection circuit 37 together with the digitized data DATAP to generate a synchronization signal SYMC. Further, this synchronization signal 5YNC is subjected to timing adjustment in a timing control circuit 38, and then sent to a 10-bit to 8-bit conversion circuit 39 together with the digitized data DATAP.
supplied to

This 10-8 conversion circuit 39 separates the input digitized data DATAP into an information signal component and the control data D component, outputs the information signal component to the error correction circuit 40, and outputs the control data D component. It is output to the address generation circuit 41. The information signal supplied to the error correction circuit 40 is subjected to predetermined error correction processing, and then
It is converted into an analog signal by a D/A (digital/analog) conversion circuit 42, and is supplied to an analog playback circuit system (not shown) via an output terminal 43, where the tape 1 is output.
The data recorded in 5 is played back.

On the other hand, the address generation circuit 41 extracts an address data component from the input control data D, and outputs it to the output terminal 4.
4 to, for example, a circuit (not shown) that performs a data search operation.

Next, the drum motor 20 is controlled by a drum servo circuit described below so that its rotational speed remains constant during recording and reproduction. That is, the drum 1
A head 45 for frequency detection and a head 46 for position detection are installed near 6. Among these, the head 45 is installed facing a rotating body (not shown) that rotates together with the drum 16 and has an AC magnetization pattern (FG pattern) for frequency detection formed thereon.
The frequency signal DFG corresponding to the rotation speed of 6 is generated. The frequency signal DFG obtained from the head 45 is transmitted to the drum servo circuit 4 via an amplifier 47.
8.

On the other hand, the heads 46 are installed facing a rotating body (not shown) that rotates together with the drum 16 and has a magnetization pattern for position detection formed thereon, and each head 18. A position signal DPG is generated as a reference for determining the position of 19. and,
The position signal DPG obtained from the head 46 is supplied to the drum servo circuit 48 via an amplifier 49 and a delay circuit 50.

Here, the drum servo circuit 48 includes each head 45,
Frequency signal DFG and position signal DPG obtained from 46
and the drum servo reference clock signal @CK generated by the clock generation circuit 24 are compared in frequency and phase, respectively, and voltage signals corresponding to the frequency difference and phase difference are added to generate the drum motor 20. It is intended to supply For this reason, the drum motor 20 is controlled to have a constant rotational speed, and the rotational speed of the drum 16 is controlled to be constant (100/31h).

Next, the rotational speed of the capstan motor 21 is controlled by a capstan servo circuit described below. That is, a frequency detection head 51 is installed near the capstan 11. This head 51 is installed facing a rotating body (not shown) which rotates together with the capstan 17 and has an AC magnetization pattern (FG pattern) for frequency detection formed thereon. Frequency signal CF corresponding to
It generates G.

Then, the frequency signal CFG obtained from the head 51 is
is connected to the capstan servo circuit 53 via the amplifier 52.
supplied to In this case, during recording, the switch circuit 5
4 is in a switching state opposite to that shown in the figure, and the reference signal K for the cab stan servo generated by the clock generation circuit 24 is the frequency signal CFG obtained from the head 51.
The signal is superimposed on the signal and supplied to the capstan servo circuit 53.

Then, the capstan servo circuit 53 compares the frequencies of the frequency signal CFG and the superimposed signal on the reference signal with the reference clock signal OK for the capstan servo generated by the clock generation circuit 24, and calculates the frequency difference. At the same time, a signal obtained by dividing the frequency of the superimposed signal and the reference clock signal CK are phase-compared, a voltage signal corresponding to the phase difference is generated, and these two voltage signals are added. , which is output to the capstan motor 21.

Therefore, the capstan motor 21 is controlled to have a constant rotational speed based on the reference clock signal CKI output from the clock generation circuit 24, and the rotational speed of the capstan 17 is constant in the recording mode. The running speed of the tape 15 is constant (8,150 mta/s
).

Further, during reproduction, the switch circuit 54 is controlled to the switching state shown in the figure, and the tracking error signal TE output from the ATF circuit 55, which will be described later, is transmitted to the head 5.
The frequency signal CFG obtained from 1 is superimposed on the frequency signal CFG and is supplied to the capstan servo circuit 53. Therefore, the capstan servo circuit 51 receives the frequency signal CF.
A superimposed signal of G and tracking error signal TE, and a reference clock signal GK output from the clock generation circuit 24
and a voltage signal corresponding to the frequency difference is generated, and the tracking error signal TE is extracted from the superimposed signal, and the tracking error signal TE is
and the reference clock signal GK, a voltage signal corresponding to the phase difference is generated, these two voltage signals are added together, and the result is output to the capstan motor 21.

Therefore, the capstan motor 20 is rotated at a constant speed, and the rotational speed of the capstan 170, that is, the running speed of the tape 15 is controlled to be constant in the playback mode.

Here, the ATF circuit 55 operates on each head 18.1 guided by the switch circuit 34, although the detailed operation will be described later.
Using the ATF data for tracking servo out of the control data D included in the reproduction signal RF from 9, each head 18, 19 and the tape 15 corresponding to it are
A tracking error signal TE corresponding to a tracking deviation with respect to a track formed above is generated.

Therefore, in the playback state, the capstan motor 2
1, the rotational speed is controlled based on the tracking error signal TE, and the running speed of the tape 15 is controlled, thereby eliminating the tracking deviation and allowing each head 18, 19 to locate the center of the corresponding track. Tracking servo is performed to ensure accurate tracing.

Further, the rotational speed of the reel motors 13 and 14 is controlled by a reel servo circuit described below. That is, in a normal recording/reproduction state, the switch circuit 56 is controlled to a switching state opposite to that shown in the figure, and a tape speed detection signal output from the tape speed detection circuit 57 is supplied to the reel servo circuit 58. This tape speed detection circuit 57 receives reproduction signals RF from each head 18 and 19 obtained via the switch circuit 34.
The running speed of the tape 15 is detected by extracting periodic data components from the control data D contained therein.

Then, the reel servo circuit 58 causes each reel motor 13. A driving signal is generated, the reel stands 11 and 12 are driven to rotate at a predetermined rotational speed, and the tape 15 is supplied from the reel stand 11 and the tape 15 is wound up by the reel stand 12.

On the other hand, in a search state in which the tape 15 is run at high speed and data is read, the switch circuit 5G is controlled to the illustrated switching state. Here, heads 59 and 60 for frequency detection are installed near the drill stands 11 and 12, respectively. These heads 59 and 60 are installed facing a rotating body (not shown) which rotates together with the reel stand 11 and 12 and has an AC magnetization pattern (FG pattern) for frequency detection formed thereon. 11.1
A frequency signal RFG corresponding to the rotation speed of 2 is generated respectively.

The frequency signals RFG obtained from each of the heads 59 and 60 are supplied to the reel servo circuit 58 via amplifiers 61 and 62 and switch circuits 56, respectively.

Then, the reel servo circuit 58 controls each head 59.60.
Based on the frequency signal RFG obtained from the tape 15
The running speed is calculated, and the rotational speed of the reel motor 13, 14 is controlled based on the reel servo reference clock signal CK output from the clock generation circuit 24, so that the tape 15 is run at a constant speed. It is controlled as follows.

Here, the running speed of the tape 15 in the search state is:
A speed at which the heads 18 and 19 can stably read data is set in advance, and the speed is controlled to the set speed.

Next, FIG. 4 shows the format of tracks formed on the tape 15. In other words, one track consists of 196 blocks, with 12 blocks in the center.
Eight blocks serve as a data area in which digitized data converted into PCM is stored. Further, the control data D is recorded on both sides of this data area.

Here, the control data D is 11 from the left side in FIG.
Block margin data MARGIN.

2 blocks of PLL data, 8 blocks of subcode data, 5UB1.1 block of postamble data PA
, 3 blocks of IBG data, 5 blocks of ATF data, 3 blocks of IBG data, and 2 blocks of PLL
Data is recorded in order.

The control data D includes, from the right side in FIG. 4, 11 blocks of margin data MARGIN, 1 block of postamble data PA, 8 blocks of subcode data 5UB2, 2 blocks of PLL data, 3 blocks of IBG data, The data is recorded in the order of 5 blocks of ATF data and 3 blocks of IBG data.

In the data area, digitized data is recorded after being converted from 8-bits to 10-bits and NRZ (non-return-to-zero) modulated.

Further, the subcode data 5UB1.5UB2 is a position information signal indicating the song number, absolute time, etc.

Furthermore, the PLL data is the subcode data 5.
UB1.5UB2 and the data handling clock signal P
This is an information signal for generating LCK, fch/2(
fch is a single wave with a data rate of >9,408 MHz. Furthermore, the above margin data MARGIN and postamble data PA are each f ch/2
The IBG data is a single wave of f ah/6.

Here, the above-mentioned one block has 36 blocks as shown in FIG.
It is made up of symbols. Of these, 28 in the center
The symbol is a data area in which digitized data is stored. Also, on the left side of this data area in the figure, 4
Symbol control data is recorded, and four symbols of parity data pa are recorded on the right side of the data area in the figure.

The above one symbol consists of 8 bits,
The control data of the above four symbols is as shown in FIG.
1 symbol of sync data 5YNC, 2 symbols of word W1. It consists of W2 and one symbol of parity data Pb. Here, word W1 is the number of channels and emphasis.

It shows the track pitch width, frame address, etc., and word W2 shows the block address.

Further, the ATF data is transmitted to the track corresponding to the head 18 by a synchronization (SYNC) signal 81, as shown in FIG.
(fch/18) and a pilot signal (shown in a grid pattern in the figure) P (single wave of fch/72) are formed, and a synchronization signal 82 (
fch/12) and a pilot signal P (shown in a grid pattern in the figure).

In FIG. 7, arrows 18 and 19 indicate the moving direction of the heads 18 and 19, and arrow C indicates the running direction of the tape 15.

Next, the tracking servo will be explained. This tracking servo is generally an area-divided ATF.
(Automatic Track Finding) system is adopted, and among these, a 4-track self-contained system is actually used.

In other words, the second track from the top in FIG.
Consider that 9 traces. First, when the head 19 reaches the recorded portion of the synchronization signal S2, the ATF circuit 55 detects the reproduction signal R from the head 19 based on the frequency.
It is determined that F is being supplied and that it is the synchronizing signal S2.

Then, the ATF circuit 55 detects the adjacent track (1 in FIG. 7) at the timing when the synchronization signal S2 is detected.
The level at which the head 19 reproduces the pilot signal P leaking from the top track is detected. Next, the ATF circuit 55 detects the pilot signal P leaking from the adjacent track (the third track from the top in FIG. 7) by the head 19 at a timing when a predetermined period of time has elapsed since the synchronization signal S2 was detected. Detect the level played. and,
The ATF circuit 55 calculates the difference in the level of leakage between the detected pilot signals, and calculates the tracking error corresponding to which side of the adjacent track the head 19 is biased from the center of the track to be traced. A signal TE is generated.

Thereafter, the capstan motor 21 is controlled as described above based on the tracking error signal TE generated as described above, and the running speed of the tape 15 is controlled, thereby performing tracking servo. be.

Next, the relationship between the rad floater signal HDCKP for reproduction and the reproduction signal RF obtained from the heads 18 and 19 will be explained. That is, FIG. 8(a) shows the reproduction RAD clock signal HDCKP, and during the period when this signal is at H level, the switch circuit 34 controls the reproduction signal obtained from the head 18, as shown in FIG. 8(b). The switch circuit 34 is switched to guide the signal RFa to the data slice circuit 35, and during the L level period, the switch circuit 34 is switched to guide the reproduced signal RFb obtained from the head 19 to the data slice circuit 35.

Then, the RAD clock signal 1-1 of IDcKP for reproduction.
The period corresponds to one rotation of the drum 16, and the reproduction signals RFa and RFb from each head 18° 19 are obtained approximately at the center of the H level and L level period of the reproduction rad float signal HDCKP. is being done.

Here, the reproduction signal RFa from each head 18 and 19.

A pair of RFb's constitute one frame, and the frame address of word W1 mentioned above indicates the position of this frame. Therefore, when the drum 16 rotates once, the frame addresses of all the words W1 included in the reproduced signals RFa and RFb obtained from the heads 18 and 19 have the same value.

Note that the recording clock signal HDCKR also outputs digitized data to the head 18 during its H level period.
The switch circuit 25 is switched to supply the digitized data to the head 19 during the L level period. The relationship between the recording clock signal HDCKR and the digitized data supplied to the heads 18 and 19 is substantially the same as described above.

However, in the conventional digital recording and reproducing apparatus as described above, since the running speed of the tape 15 in the search state is set to a constant value, the search time is specified, and there is a desire to speed up the search more than the current situation. This is something that cannot be done. In particular, the running speed of the tape 15 in the search state is set at a speed that allows the heads 18 and 19 to read data stably. Even if the data can be read by performing the above steps, the tape speed is actually set to be 150 times faster for safety purposes, which further impedes the speed of the search.

(Problems to be Solved by the Invention) As described above, in the search means provided in the conventional digital playback device, the tape running speed is suppressed.
The problem is that a faster search operation cannot be expected.

Therefore, this invention was made in consideration of the above circumstances, and provides an extremely good data search circuit for a digital playback device that can realize the fastest possible search and shorten the search time. The purpose is to provide.

[Structure of the Invention] (Means for Solving the Problems) That is, the data search circuit of the digital playback device according to the present invention detects the error occurrence rate of data read in the search state, and detects the error occurrence rate when the error occurrence rate reaches a predetermined value. The drive speed of the recording medium is increased until it reaches a level or higher.

(Function) According to the above configuration, the driving speed of the recording medium is increased until the error occurrence rate of data read in the search state exceeds a predetermined level, so that the search cannot be performed as before. The tape running speed at the time is not specified as constant, and the highest possible search speed can be realized, and the search time can be shortened.

(Example) Hereinafter, a practical example of the present invention will be described in detail with reference to the drawings. In FIG. 1, the same parts as in FIG. 3 are indicated by the same symbols, and only the different parts will be described here. That is, in a normal tape playback state, the reel servo circuit 58 is controlled by the speed detection signal of the tape 15 detected by the tape speed detection circuit 57 based on the playback signal RF obtained from each head 18, 19.
Reel motors 13, 14 are rotationally driven.

In the search state, the detection circuit 63 detects the number m of blocks in which no errors occur among the n blocks of the reproduced digitized data based on the error correction process of the error correction circuit 40. Then, depending on whether the number m of blocks in which no error has occurred is greater or less than a predetermined value, the reel servo circuit 58 is controlled to control the rotational speeds of the reel motors 13 and 14, and the tape 1
The vehicle is designed to adjust the traveling speed of No. 5.

The operation of the above configuration will be described below with reference to the flowchart shown in FIG. First, when the process is started (step S1), it is determined in step $2 whether or not a search has been requested, and if it has not been requested (No), II is completed (step 510).

Also, if a search is requested in step S2 (Y
ES), in step S3, the number m of error-free blocks detected by the detection circuit 63 satisfies m≦m1.
...(1) (where ml is a value close to the above n) It is determined whether or not. If the above formula (1) is not satisfied (No), it means that an error has occurred in most of the n blocks. in,
Processing for unrecorded tape is performed and the process ends (step 51).
0) to be done.

On the other hand, if the above equation (1) is satisfied in step S3, then (
YES), in step S5, the reel servo circuit 58
The mode is switched so as to be controlled based on the detection signal from the detection circuit 63 without being affected by the detection signal from the tape speed detection circuit 57. Thereafter, in step S6, it is determined whether the search has ended or not. If the search has ended (YES), it is ended in step S10, and if the search has not ended (
No), in step S7, m≧m2...(2) (however, m
2 is a value set based on the judgment that if the number m of error-free blocks becomes smaller than this, accurate search operation will not be possible. If the above formula (2) is satisfied (YES), a sufficiently accurate search operation can be performed even if the tape running speed is further increased, so in step S8, the reel servo circuit 58 controls the reel motor 1
3.14 is increased, and the running speed of the tape 15 is controlled to be increased.

Further, if the above formula (2) is not satisfied (No), if the tape running speed is increased any further, a sufficiently accurate search operation will not be possible, so in step S9, the reel servo circuit 58 switches the reel motor 13° 14 The rotational speed of the tape 15 is reduced, and the running speed of the tape 15 is controlled to be slowed down.

Therefore, according to the configuration of the above embodiment, since the tape running speed is controlled according to the number m of error-free blocks among n blocks of reproduced digitized data, no errors occur. As long as the data can be read, the tape speed can be increased and a quick search operation can be realized.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] Therefore, as detailed above, according to the present invention, data of an extremely good digital playback device can be realized, which can realize the fastest possible search and shorten the search time. A search circuit can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data search circuit of a digital playback device according to the present invention, FIG. 2 is a flowchart for explaining the operation of the same embodiment, and FIG. 3 is a conventional digital playback device. 4 to 6 are diagrams for explaining the format of data recorded on one track, respectively.
The figure shows the details of the ATF data, and FIG. 8 is a timing diagram showing the relationship between the rad clock signal for reproduction and the reproduction signal obtained from the head. 11, 12... Reel stand, 13.14... Reel motor, 15... Tape, 16... Drum, 17...
・Capstan, 18°19...Head, 20...
Drum motor, 21... Capstan motor, 22...
...Input terminal, 23... Recording signal generation circuit, 24...
・Clock generation circuit, 25... Switch circuit, 26° 27... Gate circuit, 28.29... Input terminal, 3
0.31...Amplifier, 32.33...Equalizer circuit, 34...Switch circuit, 35...Data slice circuit, 36...PLL circuit, 37...Synchronization signal protection circuit, 38... ...timing control circuit, 39...1
0-8 conversion circuit, 40... error correction circuit, 41...
・Address generation circuit, 42...D/A conversion circuit, 43
．． 44...Output terminal, 45.46...Head, 47
...Amplifier, 48...Drum servo circuit, 49...
・Amplifier, 50...Delay circuit, 51...Head, 5
2...Amplifier, 53...Capstan servo circuit,
54... Switch circuit, 55... ATF circuit, 56
...Switch circuit, 57...Tape speed detection circuit, 58...Reel servo circuit, 59.60...Head, 61.62...Amplifier, 63...Detection circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 2

Claims (1)

[Claims] A digital device that reads the digital data by driving a recording medium on which digital data with positional information is recorded at a predetermined speed, and reads the digital data by driving the recording medium at high speed and performs a data search based on the positional information. In the data search circuit of the playback device, there is provided a detection means for detecting an error occurrence rate of the digital data read in the data search state, and a drive speed of the recording medium until the error occurrence rate determined by the detection means reaches a predetermined level or higher. 1. A data retrieval circuit for a digital playback device, characterized in that the data retrieval circuit comprises a driving means for increasing the amount of data.