JPS6257173A - Digital signal reproducing control device - Google Patents

Digital signal reproducing control device

Info

Publication number
JPS6257173A
JPS6257173A JP19629285A JP19629285A JPS6257173A JP S6257173 A JPS6257173 A JP S6257173A JP 19629285 A JP19629285 A JP 19629285A JP 19629285 A JP19629285 A JP 19629285A JP S6257173 A JPS6257173 A JP S6257173A
Authority
JP
Japan
Prior art keywords
circuit
pll
signal
error signal
digital signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19629285A
Other languages
Japanese (ja)
Inventor
Katsuhisa Nishimura
西村 勝壽
Akihiro Nakatani
明弘 中谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP19629285A priority Critical patent/JPS6257173A/en
Publication of JPS6257173A publication Critical patent/JPS6257173A/en
Pending legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To reproduce a normal clock by moving automatically leading-in of a phase locked loop PLL, by supplying an error signal of a rotation control system to the PLL circuit control system of a self-clock circuit. CONSTITUTION:A rotary system controlling circuit 5 and a PLL circuit 2 are connected through a signal correcting circuit 8. In this state, a torque variation which appears in a rotary system such as a motor, etc. under the condition that a large jitter is generated is detected as an error signal by a detecting circuit 7, and this error signal is corrected to a correct state by the circuit 8, and thereafter, applied to the circuit 2. In this way, a leading-in range of the PLL can be moved automatically, and a normal clock reproduction can be executed.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はデジタル音響機器等に使用するデジタル信号再
生制御装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital signal reproduction control device used in digital audio equipment and the like.

従来の技術 近年、音響機器は、急速にデジタル化が進み、特にコン
パクトディスク(an)と呼ばれるものの普及は著しい
BACKGROUND OF THE INVENTION In recent years, digitalization of audio equipment has progressed rapidly, and in particular, compact discs (AN) have become widespread.

一方、磁気テープを用いるデジタル記録再生機器も実用
化が進み、CDプレーヤと共に将来はアナログ音響機器
の分野に深く浸透していく気配である。
On the other hand, digital recording and reproducing devices using magnetic tape are also being put into practical use, and there are signs that they will penetrate deeply into the field of analog audio equipment in the future, along with CD players.

さらに機器の小型軽量化を達成するための各種技術開発
が進むと共に、上述した機器は携帯型も出まわシ始めた
Furthermore, as various technological developments have progressed to make devices smaller and lighter, portable types of the above-mentioned devices have also begun to appear.

一般的にデジタル機器の再生制御装置においては、デー
タ読出し用のクロックをデータの中から抽出し、それを
使ってビットを抜出す、いわゆるセルフクロックという
技術を使っており、代表的なセルフクロック回路として
はフヱーズ・ロックド・ループ(PLL)が用いられて
いる。これによって再生信号検出用ピックアップ手段(
磁気ヘッドも含む)と、データ記録媒体間の相対速度変
動によって生ずる再生信号の時間軸変動が、はとんど復
調への影響を与えなくなっている。
Generally, playback control devices for digital equipment use a so-called self-clock technology, which extracts a clock for reading data from data and uses it to extract bits.A typical self-clock circuit For this purpose, phase locked loop (PLL) is used. This allows the reproduction signal detection pickup means (
Fluctuations in the time axis of the reproduced signal caused by fluctuations in the relative speed between the data recording medium (including the magnetic head) and the data recording medium have almost no effect on demodulation.

発明が解決しようとする問題点 ところが、前述の如く機器のポータプル化が進むにつれ
て機器が受ける外乱は複雑となり、例えば振動等で再生
音の音飛び、ひずみ、雑音等が発生するようになって来
た。これは前記PLLの制御範囲を越えるような外乱が
加わり、正常なりロック再生が出来ないためにエラーを
発生するものであり、ポータプル機器としては致命的な
問題となっていた。
Problems to be Solved by the Invention However, as mentioned above, as devices become more portable, the disturbances that devices receive become more complex, and for example, vibrations can cause skipping, distortion, noise, etc. in the reproduced sound. Ta. This is because a disturbance exceeding the control range of the PLL is added, and normal or lock playback is not possible, resulting in an error, which is a fatal problem for portable devices.

本発明は上記問題点に鑑み、振動等の外乱によってモー
タ等の回転系に速度変動を生じた時、デジタル信号再生
系内のセルフクロック回路を構成しているPLL回路の
制御特性を変えて、外乱に対する追随特性を変えるよう
にしたデジタル信号再生制御装置を提供するものである
In view of the above problems, the present invention changes the control characteristics of the PLL circuit that constitutes the self-clock circuit in the digital signal reproduction system when a speed fluctuation occurs in a rotation system such as a motor due to disturbance such as vibration. The present invention provides a digital signal reproduction control device that changes the tracking characteristics for disturbances.

問題点を解決するための手段 上記問題点を解決するために本発明のデジタル信号再生
制御装置は、デジタル信号をクロック再生するためのセ
ルフクロック回路のPLL回路制御系に、デジタル信号
記録媒体駆動用回転制御系のエラー信号を混合し得る構
成を備えたものである。
Means for Solving the Problems In order to solve the above problems, the digital signal reproduction control device of the present invention includes a PLL circuit control system of a self-clock circuit for clock reproduction of digital signals, for driving a digital signal recording medium. It is equipped with a configuration that can mix error signals of the rotation control system.

作用 本発明は上記した構成によって、外乱を受けだ回転制御
系で得られる誤差信号(エラー信号)がPLL制御系の
引込み範囲を拡大するように作用するため、再生信号に
含まれる時間軸変動(ジッタ)が通常よシも増加したと
しても、正常なりロック再生ができるようになる。
According to the above-described configuration, the error signal (error signal) obtained in the rotation control system that receives disturbance acts to expand the pull-in range of the PLL control system, so that the time axis fluctuation ( Even if the jitter increases more than usual, lock playback can be performed normally.

実施例 以下、本発明の実施例に係るデジタル信号再生制御装置
について、図面を参照しながら説明する。
Embodiment Hereinafter, a digital signal reproduction control device according to an embodiment of the present invention will be described with reference to the drawings.

図は本発明の実施例に係るデジタル信号再生制御装置の
主要部のブロック図を示すものである。
The figure shows a block diagram of the main parts of a digital signal reproduction control device according to an embodiment of the present invention.

図において、1はセルフクロック回路であシ、フェーズ
・口lクド・ループ(PLI、回路)2と波形整形回路
3とで代表的に示した。4はPCM等デジタル変調され
た復調前の信号が印加される再生信号入力端子である◇ 6は回転系制御回路であシ、ディスクや磁気テープ等の
記録媒体の駆動もしくは、信号トラックのトレースに必
要な機械駆動系の制御回路で、その中の6はモータ、7
はモータ制御系の主要部誤差信号検出回路である。
In the figure, 1 is a self-clock circuit, and a phase locked loop (PLI, circuit) 2 and a waveform shaping circuit 3 are representatively shown. 4 is a reproduction signal input terminal to which a digitally modulated signal such as PCM before demodulation is applied. ◇ 6 is a rotation system control circuit, which is used to drive a recording medium such as a disk or magnetic tape or to trace a signal track. Necessary mechanical drive system control circuit, of which 6 is the motor and 7 is the control circuit of the mechanical drive system.
is the main error signal detection circuit of the motor control system.

8は信号補正回路であり、回転系制御回路5の誤差信号
検出回路7と、PLL回路2の帰還回路9との緩衝と、
信号を混合に適した状態に補正するための回路である。
8 is a signal correction circuit, which buffers between the error signal detection circuit 7 of the rotation system control circuit 5 and the feedback circuit 9 of the PLL circuit 2;
This circuit corrects signals to a state suitable for mixing.

以上のように構成された本実施例のデジタル信号再生制
御装置において、通常は再生信号入力端子4に印加され
た信号が波形整形回路3で波形整形された後、PLL回
路2でセルフクロック作用によシクロ−Iりが抽出され
、そのクロックによってビットを抜出して、図示されて
いない復調回路へデータを転送するようになっている。
In the digital signal reproduction control device of this embodiment configured as described above, normally, after the signal applied to the reproduction signal input terminal 4 is waveform-shaped by the waveform shaping circuit 3, the signal is subjected to self-clocking by the PLL circuit 2. The clock signal is extracted, the bits are extracted using the clock, and the data is transferred to a demodulation circuit (not shown).

通常、PI、Lの制御引込み範囲は中心周波数に対して
少なくとも数パーセントはあるため、入力信号のわずか
なジ9夕に対しては充分追随し得ることができる。しか
し、ジッタが大きくなってくると、PLLの制御範囲を
逸脱するため、本発明ではそのような事態の発生を防ぐ
ために、回転系制御回路5とPLL回路2を信号補正回
路8を介して接続する構成をとっている。すなわち、大
き 。
Normally, the control pull-in range of PI and L is at least several percent with respect to the center frequency, so it is possible to sufficiently follow even slight changes in the input signal. However, when the jitter becomes large, it deviates from the control range of the PLL, so in the present invention, in order to prevent such a situation from occurring, the rotation system control circuit 5 and the PLL circuit 2 are connected via the signal correction circuit 8. It is configured to do this. That is, large.

なジッタを生ずる条件下では、振動等の影響がモータ等
の回転系にトルク変動として現われておシ、これは、回
転系制御回路6の誤差信号検出回路7から誤差信号とし
て検出することができる。この誤差信号を信号補正回路
8で適正なる状態に補正した後、PLI、回路2に印加
することにより、PLLの制御範囲を移動させることが
可能となった。
Under conditions that cause jitter, the influence of vibrations appears as torque fluctuations in the rotating system such as a motor, and this can be detected as an error signal by the error signal detection circuit 7 of the rotating system control circuit 6. . After this error signal is corrected to an appropriate state by the signal correction circuit 8, it is applied to the PLI circuit 2, thereby making it possible to move the control range of the PLL.

発明の効果 以上のように本発明は、デジタル信号再生装置のセルフ
クロック回路のPLL制御系に、回転制御系の誤差信号
を供給するように構成したため、外乱によって再生デー
タが大きな時間軸変動を受けた場合でも、PLLの引込
範囲を自動的に移動させることが可能になシ、この結果
、携帯型音響機器に用いた場合は、振動等の影響を受け
た場合でも音飛びや雑音の発生を著しく減少させること
が可能となる等、その効果は非常に大きいものがある。
Effects of the Invention As described above, the present invention is configured so that the error signal of the rotation control system is supplied to the PLL control system of the self-clock circuit of the digital signal reproducing device. As a result, when used in portable audio equipment, it is possible to automatically move the PLL pull-in range even when the PLL is affected by vibrations, etc.. The effects are very large, such as making it possible to significantly reduce the amount of water.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の実施例を示す主要部のブロック図である。 1・・・・・・セルフクロック回路、2・・曲P L 
L 回路、3・・・・・・波形整形回路、6・・面回転
系制御回路、8・・・・・・信号補正回路、。
The figure is a block diagram of main parts showing an embodiment of the present invention. 1... Self-clock circuit, 2... Song P L
L circuit, 3... Waveform shaping circuit, 6... Surface rotation system control circuit, 8... Signal correction circuit.

Claims (1)

【特許請求の範囲】[Claims] デジタル信号をクロック再生するためのセルフクロック
回路のフェーズ・ロックド・ループ回路制御系に、デジ
タル信号記録媒体駆動用回転制御系のエラー信号を信号
補正回路を介して混合するように構成し、外乱に応じて
前記フェーズ・ロックド・ループ回路の引込み範囲を自
動的に移動させるようにしたことを特徴とするデジタル
信号再生制御装置。
The phase-locked loop circuit control system of the self-clock circuit for clock reproducing digital signals is configured to mix the error signal of the rotation control system for driving the digital signal recording medium via the signal correction circuit, and is designed to prevent disturbances. A digital signal reproduction control device, characterized in that the pull-in range of the phase-locked loop circuit is automatically moved accordingly.
JP19629285A 1985-09-05 1985-09-05 Digital signal reproducing control device Pending JPS6257173A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19629285A JPS6257173A (en) 1985-09-05 1985-09-05 Digital signal reproducing control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19629285A JPS6257173A (en) 1985-09-05 1985-09-05 Digital signal reproducing control device

Publications (1)

Publication Number Publication Date
JPS6257173A true JPS6257173A (en) 1987-03-12

Family

ID=16355374

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19629285A Pending JPS6257173A (en) 1985-09-05 1985-09-05 Digital signal reproducing control device

Country Status (1)

Country Link
JP (1) JPS6257173A (en)

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