JPS638129Y2 - - Google Patents

Info

Publication number
JPS638129Y2
JPS638129Y2 JP1981136994U JP13699481U JPS638129Y2 JP S638129 Y2 JPS638129 Y2 JP S638129Y2 JP 1981136994 U JP1981136994 U JP 1981136994U JP 13699481 U JP13699481 U JP 13699481U JP S638129 Y2 JPS638129 Y2 JP S638129Y2
Authority
JP
Japan
Prior art keywords
pellet
lead
lead frame
silicon
debris
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1981136994U
Other languages
Japanese (ja)
Other versions
JPS5840842U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1981136994U priority Critical patent/JPS5840842U/en
Publication of JPS5840842U publication Critical patent/JPS5840842U/en
Application granted granted Critical
Publication of JPS638129Y2 publication Critical patent/JPS638129Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75302—Shape
    • H01L2224/75303—Shape of the pressing surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Description

【考案の詳細な説明】 この考案はの半導体装置製造のペレツトマウン
ト工程における製造装置に関する。DETAILED DESCRIPTION OF THE INVENTION This invention relates to a manufacturing apparatus in a pellet mounting process for manufacturing semiconductor devices.

一般に、トランジスタやICなどの半導体装置
はリードフレームをペレツトマウント工程やワイ
ヤボンデイング工程などに間歇送りして製造され
る。例えば、第１図にリードフレーム１の一例を
示し、これを使つたペレツトマウント工程を第２
図の装置でもつて説明すると、第１図のリードフ
レーム１は複数の半導体装置におけるリード２と
被ペレツトマウント基板、例えば放熱板３をタイ
バー部４で一連一体化したものである。また第２
図の５はヒーター６を内蔵する搬送路、７は搬送
路５上を囲うカバーで、搬送路５はリードフレー
ム１を加熱しながらリードフレーム１をその長手
方向に間歇送りするものである。前記カバー７は
搬送路５上を不活性ガス、例えば窒素ガス雰囲気
に保つて、ペレツトマウントの熱処理時における
半田やリードフレーム１の酸化防止を行うもの
で、天面に窒素ガス８の供給穴９と半田１０の供
給穴１１、及び半導体ペレツト（以下単にペレツ
トと称する）１２の供給穴１３を一列に有する。 Generally, semiconductor devices such as transistors and ICs are manufactured by intermittently sending a lead frame through a pellet mounting process, wire bonding process, etc. For example, an example of a lead frame 1 is shown in Fig. 1, and the pellet mounting process using this is shown in the second
To explain the apparatus shown in the figure, the lead frame 1 shown in FIG. 1 is a structure in which leads 2 of a plurality of semiconductor devices and a substrate to be pellet mounted, such as a heat sink 3, are integrated in series using tie bars 4. Also the second
Reference numeral 5 in the figure denotes a conveyance path incorporating a heater 6, 7 a cover surrounding the conveyance path 5, and the conveyance path 5 intermittently feeds the lead frame 1 in its longitudinal direction while heating the lead frame 1. The cover 7 maintains an inert gas atmosphere, such as nitrogen gas, over the conveyance path 5 to prevent oxidation of the solder and lead frame 1 during heat treatment of the pellet mount, and has a nitrogen gas supply hole 8 on the top surface. 9, a supply hole 11 for solder 10, and a supply hole 13 for semiconductor pellets (hereinafter simply referred to as pellets) 12 are arranged in a row.

リードフレーム１が搬送路５上を間歇送りされ
て、１つの放熱板３が半田供給穴１１の下方定ポ
ジシヨンP1にくると、この放熱板３の被ペレツ
トマウント位置上に真空吸着ペン１４で吸着され
たチツプ状の定量半田１０が供給される。このチ
ツプ状の半田１０は次のペレツト供給穴１３の下
方定ポジシヨンP2に移行する間に、搬送路５で
加熱されたリードフレーム１によつてその融点で
ある約420゜〜450℃に加熱されて溶ける。そして、
放熱板３がポジシヨンP2にくると、第３図及び
第４図に示すようにペレツト１２を真空吸着した
コレツト１５が供給穴１３を下降してペレツト１
２を放熱板３上の溶融半田１０に所定の荷重で押
し付け、更に横に数回スクラブさせてペレツト１
２の半田付けを行う。このペレツトマウントに使
用するコレツト１５は下面にペレツトサイズに応
じた形状の凹部１６を有し、この凹部１６の内側
面はテーパ状に形成されている。ペレツト１２は
この凹部１６のテーパ内側面に上端エツジ部を当
接させて吸着される。 When the lead frame 1 is intermittently fed on the conveyance path 5 and one heat sink 3 comes to a fixed position P1 below the solder supply hole 11, a vacuum suction pen 14 is placed on the pellet mounting position of the heat sink 3. A fixed amount of solder 10 in the form of chips is supplied. This chip-shaped solder 10 is heated to its melting point of about 420° to 450°C by the heated lead frame 1 in the conveyance path 5 while moving to the lower fixed position P 2 of the next pellet supply hole 13. and melt. and,
When the heat dissipation plate 3 comes to position P2 , the pellet 15, which has vacuum-adsorbed the pellet 12, descends through the supply hole 13 and collects the pellet 1, as shown in FIGS. 3 and 4.
2 onto the molten solder 10 on the heat sink 3 with a predetermined load, and then scrub it horizontally several times to form the pellet 1.
Perform step 2 soldering. The collet 15 used for this pellet mount has a recess 16 on its lower surface having a shape corresponding to the pellet size, and the inner surface of this recess 16 is formed into a tapered shape. The pellet 12 is attracted by bringing the upper edge into contact with the tapered inner surface of the recess 16.

このようにペレツトマウントされたリードフレ
ーム１はそのまま次のワイヤボンデイング工程に
送られて、第５図に示すようにペレツト１２の表
面電極と対応するリード２の一端部上とに、金線
やアルミニウム線などのワイヤ１７がボンデイン
グされる。そして、ワイヤボンデイングが完了し
たリードフレーム１は次の樹脂モールド工程に送
られて、図示しないが放熱板３を、囲む要所が樹
脂封止される。 The pellet-mounted lead frame 1 is sent as it is to the next wire bonding process, and as shown in FIG. A wire 17 such as an aluminum wire is bonded. Then, the lead frame 1 on which wire bonding has been completed is sent to the next resin molding process, and important parts surrounding the heat sink 3 are sealed with resin (not shown).

ところで、リードフレーム１の上面にはペレツ
ト１２のマウント性やワイヤ１７のボンデイング
性を良好にするため金メツキ層１８が予め形成さ
れていることが多い。またペレツト１２はシリコ
ンのウエーハに複数個が一括して形成されてか
ら、個々に細分割されて得られる。このシリコン
のペレツト１２を金メツキ処理したリードフレー
ム１にマウントすると、次のトラブルが発生する
ことがある。 Incidentally, a gold plating layer 18 is often previously formed on the upper surface of the lead frame 1 in order to improve the mounting properties of the pellets 12 and the bonding properties of the wires 17. Further, the pellets 12 are obtained by forming a plurality of pellets on a silicon wafer at once, and then dividing the pellets into individual pellets. When this silicon pellet 12 is mounted on a gold-plated lead frame 1, the following trouble may occur.

即ち、シリコンのペレツト１２は機械的に脆
く、これをペレツトマウント時にコレツト１５で
吸着すると、コレツト１５に直接に当るペレツト
１２の上端エツジ部が砕けてシリコン屑が生じる
ことがある。このシリコン屑はコレツト１５でペ
レツト１２を放熱板３上の半田１０に押し付ける
際に特に生成し易く、この時のシリコン屑は窒素
ガス８の流れに乗つて周辺に飛散してリード２上
に付着することがある。このようなシリコン屑は
数ミクロン程度の極微細なものであるため、その
ままの状態でリード２上に付着している段には問
題ないが、ペレツトマウント時にリード２も放熱
板３とほぼ同じ温度（420〜450℃）に加熱され、
而もこの温度は金−シリコン共晶化温度（350゜〜
360℃）以上であるため、シリコン屑がリード２
の金メツキ層１８と反応してリード２上に金−シ
リコン共晶合金層が生成されることがある。この
金−シリコン共晶合金層は共晶化の時点で広範囲
に拡がり、これがリード２上のワイヤボンデイン
グ位置にできると、この位置でのワイヤ１７のボ
ンデイングができず、またボンデイングができて
もボンデイング強度が極端に低下して樹脂モール
ド時に剥れたりすることがある。このようなシリ
コン屑による半導体装置の不良品発生率は約0.2
〜0.3％ほどあり、信頼性を悪くしていた。 That is, the silicon pellet 12 is mechanically brittle, and if it is adsorbed by the collect 15 during pellet mounting, the upper edge of the pellet 12 that directly contacts the collect 15 may break, producing silicone debris. This silicon dust is particularly likely to be generated when the pellet 12 is pressed against the solder 10 on the heat sink 3 by the collect 15, and at this time, the silicon dust is carried by the flow of nitrogen gas 8, scatters to the surrounding area, and adheres to the lead 2. There are things to do. Since such silicone debris is extremely fine, on the order of several microns, there is no problem with the layer that is attached to the lead 2 as it is, but when the pellet is mounted, the lead 2 is almost the same as the heat sink 3. heated to a temperature (420-450℃),
However, this temperature is the gold-silicon eutectic temperature (350° ~
(360°C) or higher, silicone debris may be removed from lead 2.
A gold-silicon eutectic alloy layer may be formed on the lead 2 by reacting with the gold plating layer 18 of the lead 2 . This gold-silicon eutectic alloy layer spreads over a wide area at the time of eutecticization, and if it forms at the wire bonding position on the lead 2, the wire 17 cannot be bonded at this position, and even if bonding is possible, the bonding will not be possible. The strength may be extremely reduced and it may peel off during resin molding. The incidence of defective products in semiconductor devices due to such silicon waste is approximately 0.2
It was about ~0.3%, making reliability worse.

本考案はかかるシリコン屑の問題点に鑑み、こ
れを解決したもので、ペレツトマウント時にシリ
コン屑が発生して飛散してもリード上には付着し
ないように保護板をコレツト側に取付けた製造装
置を提供する。以下、本考案を各実施例でもつて
説明する。 This invention has been developed in view of the problem of silicone debris, and has been developed by attaching a protective plate to the collector side to prevent silicone debris from adhering to the leads even if they are generated and scattered during pellet mounting. Provide equipment. Hereinafter, the present invention will be explained with reference to each embodiment.

例えば、上記リードフレーム１にペレツト１２
をマウントする装置に適用した第１実施例を第６
図及至第８図を参照して説明する。この図面で明
らかなように、本考案はコレツト１９の両側面に
下方に延びて突出する２枚の保護板２０を一体に
形成する。この保護板２０はコレツト１９でペレ
ツト１２を放熱板３上の溶融半田１０に押し付け
た時に、放熱板３とリード２の間に直立して両者
間を遮蔽する大きさ形状で設ける。また、この遮
蔽効果を増す目的でペレツトマウントポジシヨン
P2の搬送路５上に保護板２０の下端部が少し嵌
まり込む溝２１を設ける。 For example, pellets 12 are placed on the lead frame 1.
The first embodiment, which is applied to a device that mounts the
This will be explained with reference to the figures to FIG. As is clear from this drawing, the present invention integrally forms two protective plates 20 on both sides of the collet 19, extending downward and protruding. The protective plate 20 is sized and shaped so that when the pellet 12 is pressed against the molten solder 10 on the heat sink 3 by the collector 19, it stands upright between the heat sink 3 and the lead 2 to shield the space between them. In addition, the pellet mount position is used to increase this shielding effect.
A groove 21 into which the lower end of the protection plate 20 is slightly fitted is provided on the conveyance path 5 of P2 .

上記コレツト１９によるペレツトマウント動作
時に、ペレツト１２の上端エツジ部が砕けてシリ
コン屑が発生して周囲に飛散したとすると、この
シリコン屑は保護板２０で遮られてリード２の方
向にはほとんど飛散しない。従つてリード２上に
シリコン屑が付着する率が極端に低下し、後のワ
イヤボンデイングは安定した良好な条件下で行え
る。また、保護板２０を２枚対向させて配置する
だけでは、この２枚の間からシリコン屑が抜け出
てリード２側へ流れる恐れがある。そこで、この
対策としてはコレツト１９の四方を囲うように保
護板を口字枠状の計４枚で構成することが有効で
ある。 If the upper edge of the pellet 12 is broken during the pellet mounting operation by the collet 19, and silicon debris is generated and scattered around, this silicon debris will be blocked by the protective plate 20 and will hardly flow in the direction of the lead 2. Does not scatter. Therefore, the rate at which silicon debris adheres to the leads 2 is extremely reduced, and subsequent wire bonding can be performed under stable and good conditions. Moreover, if only two protective plates 20 are placed facing each other, silicon debris may escape from between the two protective plates 20 and flow toward the lead 2 side. Therefore, as a countermeasure against this problem, it is effective to configure the protection plate with a total of four pieces in the shape of a mouth frame so as to surround the collet 19 on all sides.

次に第９図乃至第１１図の第２実施例を説明す
る。これはコレツト２２の両側にコレツト２２が
ペレツト１２を放熱板３上の溶融半田１０に押し
付けた時にリード２の上面に軽く接触、或は極く
近くに対向する形状の保護板２３を一体に形成し
たものである。この保護板２３はリード２の少く
ともワイヤボンデイング位置及びその近傍を保護
する大きさに設定される。この第２実施例の場
合、ペレツトマウント時にシリコン屑がリード上
空を飛散したとしても、シリコン屑は保護板２３
上に落下して、リード２上に付着することはな
い。 Next, a second embodiment shown in FIGS. 9 to 11 will be described. This is because protective plates 23 are integrally formed on both sides of the collet 22 so that when the collet 22 presses the pellet 12 against the molten solder 10 on the heat dissipation plate 3, it lightly contacts the upper surface of the lead 2 or faces very closely. This is what I did. This protective plate 23 is set to a size that protects at least the wire bonding position of the lead 2 and its vicinity. In the case of this second embodiment, even if silicon debris is scattered over the leads during pellet mounting, the silicon debris will be removed from the protective plate 23.
It will not fall upward and adhere to the lead 2.

尚、本考案は上記各実施に限定されるものでは
なく、例えば第１実施例の保護板２０と第２実施
例の保護板２３を１つにまとめた形状のものをコ
レツト側に取付けるようにしてもよい。また、本
考案はリードフレーム１以外にハーメチツクシー
ル構造のステム基板などにペレツトマウントする
ものにも十分に適用される。また保護板はコレツ
トに着脱自在に装着できるようにしてもよい。 Incidentally, the present invention is not limited to the above-mentioned embodiments. For example, the protection plate 20 of the first embodiment and the protection plate 23 of the second embodiment may be combined into one and attached to the collector side. You can. In addition to the lead frame 1, the present invention is also fully applicable to pellet mounting on a stem substrate having a hermetic seal structure. Further, the protection plate may be detachably attached to the collet.

以上説明したように、本考案によれば、リード
上にシリコン屑が付着する心配が無くなり、従つ
て常に良好なワイヤボンデイングが実現され、高
信頼度の半導体装置が提供できる。 As described above, according to the present invention, there is no need to worry about silicon debris adhering to the leads, and therefore good wire bonding can always be achieved and a highly reliable semiconductor device can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はリードフレームの一例を示す平面図、
第２図はペレツトマウント装置の一例を示す概略
断面図、第３図は第２図のＡ−Ａに沿う拡大断面
図、第４図は第３図のペレツトマウント動作時の
断面図、第５図はワイヤボンデイング後のリード
フレーム断面図、第６図及び第７図は本考案の第
１実施例を示す各動作時の要部断面図、第８図は
第６図のコレツトの斜視図、第９図及び第１０図
は本考案の第２実施例を示す各動作時での要部断
面図、第１１図は第９図のコレツトの斜視図であ
る。 ２……リード、３……被ペレツトマウント基板
（放熱板）、１２……半導体ペレツト、１９……コ
レツト、２０……保護板、２２……コレツト、２
３……保護板。 Figure 1 is a plan view showing an example of a lead frame;
FIG. 2 is a schematic sectional view showing an example of the pellet mount device, FIG. 3 is an enlarged sectional view taken along line A-A in FIG. 2, and FIG. 4 is a sectional view during operation of the pellet mount shown in FIG. FIG. 5 is a sectional view of the lead frame after wire bonding, FIGS. 6 and 7 are sectional views of essential parts during each operation showing the first embodiment of the present invention, and FIG. 8 is a perspective view of the collet in FIG. 6. 9 and 10 are sectional views of essential parts of the second embodiment of the present invention during each operation, and FIG. 11 is a perspective view of the collet shown in FIG. 9. 2...Lead, 3...Pellet mount substrate (heat sink), 12...Semiconductor pellet, 19...Collection, 20...Protection plate, 22...Collection, 2
3...Protection board.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 金メツキを施したリードを近傍に有する被ペレ
ツトマウント基板上に半導体ペレツトをコレツト
で吸着してマウントする装置であつて、ペレツト
マウント時にリードと被ペレツトマウント基板の
間に介在してリード上面を保護する保護板をコレ
ツト側に取付けたことを特徴とする半導体装置製
造装置。 This is a device that collects and mounts semiconductor pellets on a pellet mount substrate that has gold-plated leads nearby. A semiconductor device manufacturing device characterized in that a protection plate for protecting the top surface is attached to the collector side.
JP1981136994U 1981-09-14 1981-09-14 Semiconductor device manufacturing equipment Granted JPS5840842U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981136994U JPS5840842U (en) 1981-09-14 1981-09-14 Semiconductor device manufacturing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981136994U JPS5840842U (en) 1981-09-14 1981-09-14 Semiconductor device manufacturing equipment

Publications (2)

Publication Number Publication Date
JPS5840842U JPS5840842U (en) 1983-03-17
JPS638129Y2 true JPS638129Y2 (en) 1988-03-10

Family

ID=29930294

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981136994U Granted JPS5840842U (en) 1981-09-14 1981-09-14 Semiconductor device manufacturing equipment

Country Status (1)

Country Link
JP (1) JPS5840842U (en)

Also Published As

Publication number Publication date
JPS5840842U (en) 1983-03-17

Similar Documents

Publication Publication Date Title
US20180040545A1 (en) Method Of Fabricating Low Profile Leaded Semiconductor Package
CN100499104C (en) Flip chip contact(PCC) power package and package method
US6777265B2 (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
JP5089184B2 (en) Resin-sealed semiconductor device and manufacturing method thereof
US6720206B2 (en) Method for manufacturing digital micro-mirror device (DMD) packages
JP2016503240A (en) Integrated circuit module
US20020039811A1 (en) A method of manufacturing a semiconductor device
US4951120A (en) Lead frame and semiconductor device using the same
JPS60167454A (en) Semiconductor device
EP0090566B1 (en) Semiconductor device package
CN107527827B (en) Semiconductor device manufactured by fluxless soldering
KR19980067735A (en) Manufacturing method of semiconductor package
JPH05235228A (en) Method of manufacturing electronic component
JP2007134395A (en) Semiconductor device
JPS638129Y2 (en)
US4183135A (en) Hermetic glass encapsulation for semiconductor die and method
EP3955277A1 (en) Semiconductor device and method for fabricating the same
JPS63293963A (en) Resin-sealed semiconductor device
US4151638A (en) Hermetic glass encapsulation for semiconductor die and method
JPS62154769A (en) Semiconductor device
KR200179419Y1 (en) Semiconductor package
JPH02181956A (en) Semiconductor device
JPH0626222B2 (en) Die bonding method for semiconductor chips
US20100127392A1 (en) Semiconductor die
JPS60178636A (en) Semiconductor device