JPS6380723A - Controller for stational reactive power compensator - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Object of the invention] (Industrial application field) The present invention is a static var power compensator (hereinafter referred to as SVC).
The present invention relates to a control device.

(Prior Art) SvC is a reactive power supply device using a semiconductor control switch such as a thyristor, and is a device for adjusting reactive power supplied to an electric power system, etc., and stabilizing the system voltage. Fig. 3 shows an example of the configuration of a thyristor-controlled reactor (hereinafter referred to as TCR), which is an example of SvC, and a conventional control device. First, the configuration will be explained. 1-1.1-2 is a thyristor, and 2 is a reactor. 3 is the PT
, 4 is a voltage detector, 5 is a setter that indicates a reference voltage (hereinafter referred to as Vref), 6 is a subtracter, 7 is a CT, 8 is a current detector, 9 is an adder, and 10 is an integrator, and its output The current ITCR to be output from TCH is output. 11 is ITCl
Thyristor 1-1.1 such that t flows into reactor 2
12 is a PLL circuit for detecting a synchronizing signal; 13 is a firing angle determining circuit 1 for determining the firing angle α;
Thyristor 1- from the output of thyristor 1 and the output of PLL circuit 12.
This is a phase control circuit that outputs a gate pulse of 1.1-2.

Next, its effect will be explained. The grid voltage is detected by the PT 3 and the voltage detector 4 connected to the power grid, and the error voltage Δ which is the difference between the reference voltage and the grid voltage indicated by the setting device 5 is detected.
The output current of TCH is detected by the primary Cr2 and the current detector 8 where V is output by the subtracter 6, and which ΔV
and the TCH output current are added by the adder 9, and when the output passes through the integrator 10, the value of the current XTCR to be output from the TCH is determined. The firing angle α of the gate pulse of the thyristor 1-1.1-2 is determined so that the determined power τcR flows into the reactor 2. 12 is PL for synchronization detection
The L circuit receives the three-phase AC voltage of the power system from PT3 and outputs a synchronization signal, and the phase control circuit 13 receives the firing angle α, which is the output of the firing angle determining circuit 11, and the synchronization signal, which is the output of the PLL circuit 12. The signal forms a gate pulse applied to thyristor 1-1.1-2. By applying this gate pulse to the thyristor 1-1, 1-2, the current τCR output from the integrator 1° flows to the handle 2, and the voltage of the power system is stabilized.

(Problems to be Solved by the Invention) The PLL circuit 12 used in the conventional control device described above outputs a correct synchronization signal when the three-phase AC voltage of the power system is balanced, but it is not balanced. If there is no correct synchronization signal, the correct synchronization signal will not be output, and the worse the degree of imbalance, the further the synchronization signal will be output from the correct signal. Therefore, the firing angle determined by the firing angle determining circuit 11 is, for example, 90°.
If the synchronization signal output from the PLL circuit 12 is incorrect, the firing angle of the gate pulse given to the thyristor 1-1.1-2 may be 50@ or iso', for example, and the TCH Correct control will no longer be possible.

Inaccurate TCH control may make the grid voltage more unstable than without TCR, or thyristor 1-1.1
-2 An overcurrent flows through the accelerator 2, causing a problem such as destruction of the TCH or the need to stop protection.

Therefore, the purpose of the present invention is to block the gate pulse when the unbalance degree of the system aIIt pressure exceeds a predetermined value, and to control the TCH.
It is an object of the present invention to provide a control device that prevents damage to the TCR or avoids a situation where the instability of the system voltage becomes higher than in the case without a TCR.

[Structure of the Invention] ′ (Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention provides an unbalance detection circuit for detecting the unbalance of grid voltage in a conventional control device, and an unbalance detection circuit for detecting the unbalance of the system voltage. The device also includes a gate block circuit that blocks gate pulses in accordance with the output of the frequency detection circuit.

(Function) When the unbalance degree of the grid voltage is within a predetermined value, the unbalance degree detection circuit controls the gate block circuit so as not to block the gate pulse, so the gate pulse generated by the conventional control device remains as before. given to the thyristor. When the unbalance level of the grid voltage is above a predetermined value, the unbalance level detection circuit controls the gate block circuit to block the gate pulse, so the gate pulse generated by the conventional control device is not applied to the thyristor. .

(Example) An example of the present invention will be described below using FIG. 1 and FIG. Note that components having the same numbers as those used in the conventional example have the same functions.

In FIG. 1, 14 is an unbalance detection circuit, and 15 is an example of a gate block circuit, which is a switch that is closed when the output of the unbalance detection circuit 14 is at a logic level of "0" and open when it is at "1". It is. The part surrounded by the broken line A corresponds to the part of the present invention. Figure 2 shows the unbalance degree detection circuit 14 in Figure 1.
The details are shown in a three-line diagram. 16
-1.16-2.16-3 is a voltage detector, 17 is an average voltage detector, 18-1゜18-2, 18-3 is a subtractor,
19 is a setting device 20-1.20-2 that indicates a value (predetermined value) indicating the limit of the degree of imbalance;

20-3 is rOJ when the output of subtractor 18-1.18-2.18-3 is smaller than the predetermined value indicated by setting @19.
and a comparator whose output is "1" when it is larger than a predetermined value, 2
1 is an OR circuit.

Next, the operation of the embodiment will be explained. In FIG. 1, the parts explained in the conventional example are the same as the first structure and operation, and therefore will be omitted. A three-phase AC voltage signal of the power system is sent from the PT3 to the unbalance degree detection circuit 14, and when the unbalance degree of the three-phase AC voltage is below a predetermined value, the output of the unbalance degree detection circuit 14 is rOJ and the switch 15 is closed, so phase control circuit 1
The gate pulse which is the output of thyristor 3 is the output of thyristor 1-1.1-
When the unbalance degree of the five-phase three-phase AC voltage exceeds a predetermined value, the output of the unbalance degree detection circuit 14 is "1" and the switch 15 is opened. The gate pulse which is the output of the phase control circuit 13 is blocked and no gate pulse is applied to the thyristor 1-1.1-2.

Next is the 2nd v! The operation of the unbalance degree detection circuit 14 will be explained in detail using I. Unlike the single line diagram in FIG. 1, FIG. 2 depicts three phases. The three-phase AC voltage t** Vse v7 of the power system from PT3 is detected by the voltage detector 16-1.
．． 16-2.16-3 and its voltage value VR#
V B *V T is detected. On the other hand, the average voltage detector 17 detects the three-phase AC voltage vR2tF1e W from PT3.
Zero-order subtraction to detect the average value ■A from T! 18-1
.

18-2. In 18-3, the detected voltage value VR? Vse
The difference between vT and the average voltage value VA is detected, and the comparator 20-1.20-2.2 determines whether the difference voltage ΔV*atΔVSAyΔvTA is larger or smaller than a predetermined value indicated by the setter 19.
Compared 0-3. When the differential voltage ΔvR9ΔVSyΔvT is less than or equal to a predetermined value, the output is rOJ, and when it is greater than or equal to the predetermined value, it is “1”.

First, when all the differential voltages ΔVRPΔV S tΔv are below a predetermined value, the output of the OR circuit 21 is “0”, that is, the output of the unbalance degree detection circuit 14 is “0”, and the switch 15 remains closed, and the gate pulse is sent from the thyristor. 1-1.1-2. What this means is that the degree of unbalance of the system voltage is less than a predetermined value, and the synchronization signal output from the PLL circuit 12 is inaccurate enough to cause no problem, so a gate pulse is given to the thyristor.

Next, when any one of the differential voltages ΔvR2ΔVStΔvd exceeds a predetermined value, the comparator 20-1.20-2゜20-3
Since at least one of the outputs of is rlJ, OR circuit 2
The output of 1 is "1", that is, the output of the unbalance detection circuit 14 is "1", the switch 15 is opened, and the gate pulse that is the output of the phase control circuit 13 is blocked. In other words, since the degree of unbalance of the grid voltage is large, the synchronization signal output from the PLL circuit 12 is very inaccurate, and the gate pulse is blocked because there is a possibility that the problem described in the conventional technology will occur. be.

In this example, the difference voltage between each phase voltage and the average voltage was used as a means to detect the degree of unbalance, but in addition, the difference voltage between the maximum value and the minimum value of each phase voltage, the negative sequence voltage with respect to the positive sequence voltage, etc. The degree of imbalance can also be detected using the ratio of .

〔Effect of the invention〕

As explained above, if the present invention is used, when the unbalance degree of the grid voltage is below a predetermined value, a gate pulse is given to the SVC thyristor to stabilize the grid voltage, and the unbalance degree of the grid voltage becomes the predetermined value. If the value exceeds the value, block the gate pulse to the thyristor to prevent damage to the thyristor and inaccurate control of SvC to avoid situations where the grid voltage becomes more unstable than without SvC. Can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a detailed diagram of an unbalance degree detection circuit constituting an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional example. 14... Unbalance degree detection circuit 15... Switch 16... Voltage detector 17... Average voltage detector 18... Subtractor 19
...Setter 20...Comparator 21...
・OR circuit agent Patent attorney Nori Chika Yudo Hirofumi Mitsumata

Claims (1)

[Claims] A static reactive power compensator whose components are semiconductor switches controlled by gate pulses is connected to a three-phase AC system, and a Phase Loch is used as a synchronization detection circuit.
In a control device for a static var compensator using an ed Loop circuit, an unbalance detection circuit detects the unbalance degree of the voltage of the three-phase AC system, and a gate is set according to the output of the unbalance detection circuit. 1. A control device for a static reactive power compensator, comprising a gate block circuit for blocking pulses.