JPS6379348A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6379348A JPS6379348A JP61223599A JP22359986A JPS6379348A JP S6379348 A JPS6379348 A JP S6379348A JP 61223599 A JP61223599 A JP 61223599A JP 22359986 A JP22359986 A JP 22359986A JP S6379348 A JPS6379348 A JP S6379348A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- organic film
- bump electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 230000002093 peripheral effect Effects 0.000 claims abstract description 6
- 239000011347 resin Substances 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 10
- 229920001721 polyimide Polymers 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052782 aluminium Inorganic materials 0.000 abstract description 10
- 239000005022 packaging material Substances 0.000 abstract 3
- 238000000151 deposition Methods 0.000 abstract 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 7
- 229910052804 chromium Inorganic materials 0.000 description 7
- 239000011651 chromium Substances 0.000 description 7
- 239000003566 sealing material Substances 0.000 description 7
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 239000000872 buffer Substances 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 108091006146 Channels Proteins 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関するものであり、特に、半導
体装置の封止技術に適用して有効な技術に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a technique that is effective when applied to a sealing technique for a semiconductor device.
半導体装置の外部電極であるバンブ？！！極にビームリ
ードを接続する際に無機膜例えば窒化シリコン膜からな
る絶縁膜に応力が加わる。この応力を紘和するために、
有機膜例えばポリイミド膜を半導体基板上の最上層に設
けている。なお、半導体装置の封止しこ関する技術は、
例えば、ロ経マグロウヒル社発行、「口紅マイクロデバ
イス」、１９８６年４１号、ｐ８１〜ｐ９５に記載され
ている。Bumps are the external electrodes of semiconductor devices? ! ! When connecting a beam lead to a pole, stress is applied to an insulating film made of an inorganic film, such as a silicon nitride film. In order to alleviate this stress,
An organic film, such as a polyimide film, is provided as the top layer on the semiconductor substrate. The technology related to the sealing of semiconductor devices is
For example, it is described in "Lipstick Microdevice", published by McGraw-Hill, Inc., 1986, No. 41, pages 81 to 95.
本発明者は前記技ｗＩを検討した結果、次の問題点を見
出した。As a result of studying the above-mentioned technique wI, the present inventor found the following problems.
半導体装置を樹脂たとえばレジンによって封止すると、
この樹脂と有機膜との熱膨張係数の差が大きいため、有
機膜に大きな応力が加わる。これにより、有機膜がはが
れ水分が浸入する。When a semiconductor device is sealed with resin, for example,
Since the difference in coefficient of thermal expansion between the resin and the organic film is large, a large stress is applied to the organic film. This causes the organic film to peel off and allow moisture to infiltrate.
本発明の目的は、半導体装置の（ａ頼性を高めることに
ある。An object of the present invention is to improve the reliability of a semiconductor device.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本原において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this original is as follows.
すなわち、有機膜を外部電極の周辺部と、無機膜からな
る絶縁膜との間に介在させかつリング状に設ける。That is, an organic film is interposed between the peripheral portion of the external electrode and an insulating film made of an inorganic film, and is provided in a ring shape.
上記した手段によれば、ボンディング時に外部電極に加
わる応力を有機膜によって緩和することができ、また有
機膜が封止材である樹脂との間の応力によってはがれる
ことがないので、信頼性を高めることができる。According to the above-mentioned means, the stress applied to the external electrode during bonding can be alleviated by the organic film, and the organic film will not be peeled off due to the stress between it and the resin that is the sealing material, thereby increasing reliability. be able to.
以下１本発明を実例とともに説明する。The present invention will be explained below along with examples.
第１図は、本実施例の半導体チップの平面図である。 FIG. 1 is a plan view of the semiconductor chip of this example.
第１図において、１は単結晶シリコンからなる半導体基
板すなわち半導体チップであり、周辺部に外部電極であ
るバンプ電極２が複数配置しである。３は人出力バッフ
ァ回路であり、例えばＰチャネルＭ Ｉ Ｓ ＦＥＴと
ＮチャネルＭＩＳＦＥＴとで構成されている。４はＭＩ
ＳＦＥＴあるいはバイポーラトランジスタによってＲＡ
Ｍ、ＲＯＭ、論理回路等の種々の回路が構成される回路
領域である。In FIG. 1, reference numeral 1 denotes a semiconductor substrate, ie, a semiconductor chip, made of single crystal silicon, and a plurality of bump electrodes 2, which are external electrodes, are arranged around the periphery. Reference numeral 3 denotes an output buffer circuit, which is composed of, for example, a P-channel MISFET and an N-channel MISFET. 4 is MI
RA by SFET or bipolar transistor
This is a circuit area where various circuits such as M, ROM, and logic circuits are configured.
次に、バンプ電極２の具体的な構成を説明する。Next, a specific configuration of the bump electrode 2 will be explained.
第２図は、本実施例における１つのバンプ電極２の断面
斜視図である。FIG. 2 is a cross-sectional perspective view of one bump electrode 2 in this example.
第２図において、５はフィールド絶縁膜であり、半導体
チップ１の表面の酸化による酸化シリコン膜からなって
いる。フィールド絶縁膜５は、半導体チップ１の表面に
構成されている半導体素子のパターンを規定するように
形成されている。フィールド絶縁膜５の図示していない
ｎ−型ウェル領域を除いた下部には、ｐ型チャネルスト
ッパ領域６が形成しである。フィールド絶縁膜５の上に
、例えばＣＶＤによる酸化シリコン膜とリンシリケート
ガラス（ＰＳＧ）とを積層して構成した第１層目の絶縁
膜７が覆っている。絶縁膜７は１例えばＭＩＳＦＥＴの
ゲート電極と同層の導電層を覆う膜である。絶縁膜７の
上に例えばＣＶＤによるＰＳＧ膜の上に、例えばプラズ
マＣＶＤによる窒化シリコン膜を積層して構成した絶縁
膜８が設けである。絶縁膜８は５例えば半導体チップ１
上の第２層の配線を覆っている。絶縁膜８はバンプ′！
を極２の部分では選択的に除去されて開口されている。In FIG. 2, reference numeral 5 denotes a field insulating film, which is made of a silicon oxide film formed by oxidizing the surface of the semiconductor chip 1. As shown in FIG. Field insulating film 5 is formed so as to define a pattern of semiconductor elements formed on the surface of semiconductor chip 1 . A p-type channel stopper region 6 is formed in the lower part of the field insulating film 5 except for an n-type well region (not shown). The field insulating film 5 is covered with a first-layer insulating film 7 formed by stacking a silicon oxide film and phosphosilicate glass (PSG), for example, by CVD. The insulating film 7 is a film that covers, for example, a conductive layer in the same layer as the gate electrode of a MISFET. On the insulating film 7, an insulating film 8 is provided, which is formed by laminating, for example, a silicon nitride film formed by plasma CVD on a PSG film formed by CVD, for example. The insulating film 8 is 5, for example, the semiconductor chip 1.
It covers the upper second layer wiring. The insulating film 8 is a bump'!
The part of pole 2 is selectively removed and opened.
バンプ電極２は、アルミニウム層９、クロム層１１、銅
とスズの合金層（以下、単に合金層という）１２．金（
Ａ ｕ ）のバンプ１３からなっている。アルミニウム
ｊ！１９は、人出力バッファ回路３から延びる信号配線
等の配線と一体に形成されて。The bump electrode 2 includes an aluminum layer 9, a chromium layer 11, an alloy layer of copper and tin (hereinafter simply referred to as an alloy layer) 12. Money(
It consists of bumps 13 of A u ). Aluminum j! 19 is formed integrally with wiring such as signal wiring extending from the human output buffer circuit 3.
バンプ電極２の部分では信号配線より大きなパターンに
なっている。バンプ電極２におけるアルミニウム層９は
、平面が例えば四角形にされている。The bump electrode 2 portion has a larger pattern than the signal wiring. The aluminum layer 9 in the bump electrode 2 has a rectangular plane, for example.
この四角形になっているアルミニウム層９の周辺部は絶
縁膜８によって覆れている。中央部は開口されて絶縁膜
８からアルミニウム層９が露出するようになっている。The periphery of this rectangular aluminum layer 9 is covered with an insulating film 8. The central portion is opened so that the aluminum layer 9 is exposed from the insulating film 8.
クロム層１１は、バンプ電極２と絶縁膜８及び後述する
有機膜１２との被着性を良くするために設けたものであ
り、アルミニウム層９中への水分の浸入を防いでいる。The chromium layer 11 is provided to improve adhesion between the bump electrode 2 and the insulating film 8 and the organic film 12 described later, and prevents moisture from penetrating into the aluminum layer 9.
合金層１２は、バンプ（Ａｕ）とクロム層１１との被着
性を良くするために設けている。The alloy layer 12 is provided to improve adhesion between the bumps (Au) and the chromium layer 11.
バンプ１３に例えば熱圧着によってリードビーム１４（
第４図）を接続すると、そのときクロムＷＪ１１の周辺
に応力が加わりこれによって絶縁膜８にクラックを生じ
ることがある。そこで、クロム層１１の周辺部と絶縁膜
８の間に有機膜例えばポリイミド膜１０を介在させてい
る。有機膜１０は絶縁膜８等より軟くボンディング時に
加る応力を１緩衝する。The lead beam 14 (
4), stress is applied to the periphery of the chromium WJ 11, which may cause cracks in the insulating film 8. Therefore, an organic film such as a polyimide film 10 is interposed between the peripheral portion of the chromium layer 11 and the insulating film 8. The organic film 10 is softer than the insulating film 8 and the like and buffers the stress applied during bonding by 1.
ここで、第３図１；、半導体チップ１の周辺のバンプ電
極２が設けられる部分の一部を示す。なお、第３図は、
有機膜１０のパターンを解り易くするため、バンプ電極
２中のアルミニウム層９のみを示し、それ以外の導電層
を示していない。Here, FIG. 3 shows a part of the area around the semiconductor chip 1 where the bump electrodes 2 are provided. In addition, Figure 3 shows
In order to make the pattern of the organic film 10 easier to understand, only the aluminum layer 9 in the bump electrode 2 is shown, and the other conductive layers are not shown.
第３図に示したように、有機膜１ｏは、バンブ電極２の
一部であるアルミニウム層９の中央部が露出するように
リング状のパターンに形成されている。また、有機膜１
０はそれぞれのバンブ電極２に個別に設けである。すな
わち、有機膜１０は、半導体チップｌ上のバンブ電極２
の周辺にのみ設けられ、それ以外の部分では設けられて
いない。As shown in FIG. 3, the organic film 1o is formed in a ring-shaped pattern so that the center portion of the aluminum layer 9, which is a part of the bump electrode 2, is exposed. In addition, organic film 1
0 indicates that each bump electrode 2 is provided individually. That is, the organic film 10 covers the bump electrode 2 on the semiconductor chip l.
It is provided only around the area, and is not provided in other areas.
このため、バンブ電極２の周辺以外の部分では無機１漠
である絶縁膜８が露出している。Therefore, the insulating film 8, which is an inorganic material, is exposed in areas other than the periphery of the bump electrode 2.
このように構成した半導体チップ１をレジン等の樹脂に
よって封止した半導体装置の断面が第４図である。なお
、第４図は、フィールド絶縁１１ｇ５、チャネルストッ
パ領域６．クロム層１１、合金層１２を図示していない
。FIG. 4 shows a cross section of a semiconductor device in which the semiconductor chip 1 constructed in this manner is sealed with a resin such as resin. Note that FIG. 4 shows field insulation 11g5, channel stopper region 6. The chromium layer 11 and alloy layer 12 are not shown.
第４図において、１４はビームリード、１５はレジン等
の樹脂からなる封止材である。In FIG. 4, 14 is a beam lead, and 15 is a sealing material made of resin or the like.
有機膜１０は、バンブ電極２の周辺部のみに設けである
ため、封止材１５との熱膨張に伴う応力が小さく絶縁膜
８からはがれにくくなっている。Since the organic film 10 is provided only on the periphery of the bump electrode 2, the stress caused by thermal expansion with the sealing material 15 is small and it is difficult to peel off from the insulating film 8.
なお、封止材１５は絶縁膜８との間の被着性が良いため
、絶縁膜８が封止材１５との熱膨張差によってはがれる
ことはない。Note that, since the sealing material 15 has good adhesion to the insulating film 8, the insulating film 8 will not be peeled off due to the difference in thermal expansion with the sealing material 15.
以上、本実施例によれば次の効果を得ることができる。As described above, according to this embodiment, the following effects can be obtained.
（１）有機膜１０をバンブ電極２の周辺部に介在させて
いることにより、ボンディング時に加る応力が緩衝され
るので、絶縁膜８．７等の無機膜にクラック等を生じる
ことがない。(1) By interposing the organic film 10 around the bump electrode 2, the stress applied during bonding is buffered, so that cracks or the like do not occur in the inorganic film such as the insulating film 8.7.
（２）前記有機膜１０をバンブ電極２の周辺部にリング
状にしていることにより、有機膜１０が封止材１５との
熱膨張差によってはが九ることがないので、半導体装置
の信頼性を高めることができる。(2) By forming the organic film 10 in a ring shape around the bump electrode 2, the organic film 10 will not peel off due to the difference in thermal expansion with the sealing material 15, so the semiconductor device will be reliable. You can increase your sexuality.
以上、本発明を実施例にもとすき具体的に説明したが、
本発明は前記実施例に限定されるものではなく、その要
旨を逸脱しない節回において種々変更可能であることは
いうまでもない。The present invention has been specifically explained above using examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the gist thereof.
例えば、バンプ１３は半田からなるものであってもよい
。For example, the bumps 13 may be made of solder.
また、絶縁膜８は、例えばプラズマＣＶＤによる酸化シ
リコン膜、ＰＳＧ膜あるいはスピンオンガラス（ＳＯＧ
）膜であってもよい。少なくとも、無機膜であればよい
。The insulating film 8 may be a silicon oxide film, a PSG film, or a spin-on glass (SOG) film formed by plasma CVD, for example.
) It may be a membrane. At least an inorganic film may be used.
第１図は、半導体チップの平面図、
第２図は１本発明の一実施例のバンブ電極の断面斜視図
、
第３図は、半導体チップのバンブ電極が設けられている
周辺部の平面図、
第４図は、樹脂で封止した半導体装置の断面図である。
図中、１・・・半導体基板（チップ）、２・・・バンブ
電極、３・・・人出力バッファ回路、４・・・回路領域
、５・・・フィールド絶縁膜、６・・・Ｐ型チャネルス
トッパ領域、７．８・・・絶縁膜、９・・・アルミニウ
ム層、１０・・・有機膜（ポリイミド）、１１・・・ク
ロム層、１２・・・合金層、１３・・・バンブ（Ａｕ）
、ｔ４・・・リードビーム、１５・・・封止材（レジン
）。FIG. 1 is a plan view of a semiconductor chip, FIG. 2 is a cross-sectional perspective view of a bump electrode according to an embodiment of the present invention, and FIG. 3 is a plan view of the peripheral area of the semiconductor chip where bump electrodes are provided. , FIG. 4 is a cross-sectional view of a semiconductor device sealed with resin. In the figure, 1... semiconductor substrate (chip), 2... bump electrode, 3... human output buffer circuit, 4... circuit area, 5... field insulating film, 6... P type Channel stopper region, 7.8... Insulating film, 9... Aluminum layer, 10... Organic film (polyimide), 11... Chromium layer, 12... Alloy layer, 13... Bump ( Au)
, t4... Lead beam, 15... Sealing material (resin).
Claims (1)
であって、前記有機膜は、外部電極の周辺部と下の絶縁
膜との間に介在しかつリング状に設けたことを特徴とす
る半導体装置。 ２、前記有機膜の下層に窒化シリコン膜等の無機膜を有
していることを特徴とする特許請求の範囲第１項記載の
半導体装置。 ３、前記半導体装置は、レジン等の樹脂によって封止さ
れる半導体装置であることを特徴とする特許請求の範囲
第１項記載の半導体装置。 ４、前記有機膜は、ポリイミド膜であることを特徴とす
る特許請求の範囲第１項記載の半導体装置。[Claims] 1. A semiconductor device having an organic film in the uppermost layer on a semiconductor substrate, wherein the organic film is interposed between a peripheral part of an external electrode and an underlying insulating film and has a ring shape. A semiconductor device characterized in that: 2. The semiconductor device according to claim 1, further comprising an inorganic film such as a silicon nitride film under the organic film. 3. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device sealed with a resin such as resin. 4. The semiconductor device according to claim 1, wherein the organic film is a polyimide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61223599A JPS6379348A (en) | 1986-09-24 | 1986-09-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61223599A JPS6379348A (en) | 1986-09-24 | 1986-09-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6379348A true JPS6379348A (en) | 1988-04-09 |
Family
ID=16800703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61223599A Pending JPS6379348A (en) | 1986-09-24 | 1986-09-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6379348A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02220442A (en) * | 1989-02-21 | 1990-09-03 | Fuji Electric Co Ltd | Reinforced structure of protective film for semiconductor device |
| US5438222A (en) * | 1989-08-28 | 1995-08-01 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device with plural pad connection of semiconductor chip to leads |
| JP2003034367A (en) * | 2001-07-25 | 2003-02-04 | Nippon Kouatsu Electric Co | Drink container |
| US20140138818A1 (en) * | 2011-12-31 | 2014-05-22 | Alexsandar Aleksov | Organic thin film passivation of metal interconnections |
| US9368437B2 (en) | 2011-12-31 | 2016-06-14 | Intel Corporation | High density package interconnects |
-
1986
- 1986-09-24 JP JP61223599A patent/JPS6379348A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02220442A (en) * | 1989-02-21 | 1990-09-03 | Fuji Electric Co Ltd | Reinforced structure of protective film for semiconductor device |
| US5438222A (en) * | 1989-08-28 | 1995-08-01 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device with plural pad connection of semiconductor chip to leads |
| JP2003034367A (en) * | 2001-07-25 | 2003-02-04 | Nippon Kouatsu Electric Co | Drink container |
| US20140138818A1 (en) * | 2011-12-31 | 2014-05-22 | Alexsandar Aleksov | Organic thin film passivation of metal interconnections |
| US9257276B2 (en) * | 2011-12-31 | 2016-02-09 | Intel Corporation | Organic thin film passivation of metal interconnections |
| US20160155667A1 (en) * | 2011-12-31 | 2016-06-02 | Intel Corporation | Organic thin film passivation of metal interconnections |
| US9368437B2 (en) | 2011-12-31 | 2016-06-14 | Intel Corporation | High density package interconnects |
| US9583390B2 (en) | 2011-12-31 | 2017-02-28 | Intel Corporation | Organic thin film passivation of metal interconnections |
| US9824991B2 (en) | 2011-12-31 | 2017-11-21 | Intel Corporation | Organic thin film passivation of metal interconnections |
| US9922916B2 (en) | 2011-12-31 | 2018-03-20 | Intel Corporation | High density package interconnects |
| US10204851B2 (en) | 2011-12-31 | 2019-02-12 | Intel Corporation | High density package interconnects |
| US10658279B2 (en) | 2011-12-31 | 2020-05-19 | Intel Corporation | High density package interconnects |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6379348A (en) | Semiconductor device | |
| JPS6118164A (en) | Semiconductor device | |
| JPH09283525A (en) | Semiconductor device | |
| KR100744700B1 (en) | Semiconductor device | |
| JPH03136334A (en) | Outer electrode structure on semiconductor integrated circuit | |
| JPS63293930A (en) | Electrode in semiconductor device | |
| JP2016171183A (en) | Semiconductor integrated circuit | |
| JPS6352445A (en) | Semiconducotr device | |
| JPH01276673A (en) | Insulated gate semiconductor device | |
| JPS615561A (en) | Semiconductor device | |
| JPS61269333A (en) | Semiconductor device | |
| JPS63308924A (en) | Semiconductor device | |
| JP2009038140A (en) | Semiconductor device and manufacturing method thereof | |
| JPS62232147A (en) | Semiconductor device | |
| JPH0526738Y2 (en) | ||
| JPS6158248A (en) | Thin type semiconductor device | |
| JPS614265A (en) | Semiconductor integrated circuit device | |
| JPS62219541A (en) | Semiconductor device | |
| JPS6119163A (en) | Semiconductor integrated circuit | |
| JP2913766B2 (en) | Semiconductor device | |
| JPS62262458A (en) | Semiconductor integrated circuit device | |
| JPH11274221A (en) | Pad for external connection of electronic component | |
| JPS62169350A (en) | Semiconductor device and manufacture thereof | |
| JPH0230171A (en) | Semiconductor device | |
| JPH01179434A (en) | Semiconductor integrated circuit device |