JPS6377159A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To prevent a line from becoming defective at time of generating a pinhole by forming a low resistance layer led from a drain or source electrode on an operation semiconductor layer of an offset region of a gate electrode from drain or source electrode. CONSTITUTION:A gate electrode 2, a gate insulating film 3 and an operation semiconductor layer 4 having a predetermined conductivity type, and transparent electrodes 5-1, 5-2 are laminated on a transparent insulating substrate 1, and a source electrode S and a drain electrode D are sequentially formed. Thereafter, a positive resist film 7 is formed on the whole surface of the substrate 1 including the surfaces of the electrodes S, D, the film 7 is exposed with an ultraviolet light 8 incident at a predetermined oblique angle to the rear surface of the substrate 1 with the electrode 2 as a mask to form a resist film 7' having a hole offset to the electrode 2. Then, with the film 7' as a mask one transparent electrode layer end 11 of the electrode S or D exposed in the hole 10 is selectively removed. Thus, the electrodes D or S offset the gate electrode 2 and a low resistance layer 13 led therefrom are formed.

Description

Detailed Description of the Invention [Summary] In the present invention, the drain and source electrodes are made of transparent electrodes such as ITO and n'a-3t disposed below the transparent electrodes.
A resist film having an opening offset from the gate electrode is formed in a laminated structure with the H layer and exposed to parallel ultraviolet light incident obliquely from the back side of the substrate using the gate electrode as a mask. The resist film is formed on the source electrode, and then, using this resist film as a mask, the end portion of the ITO layer in the upper layer of the drain electrode or source electrode exposed in the opening is selectively removed. In this way, a drain or source electrode offset with respect to the gate electrode and a low resistance layer led out from the electrode are formed.

[Industrial application field]

The present invention relates to a method for manufacturing a thin film transistor (TPT) used for driving a display device such as a liquid crystal or an electroluminescent device.

[Conventional technology]

To drive the above display device, these TFTs are
Directional integrated matrices are used, but these need to be integrated without shorting defects.

This is because even if a short-circuit defect exists at one point, all pixels on the gate electrode pass line and drain pass line connected to that point become defective, which is a serious defect.

FIG. 3 shows a structural example of a conventional TPT using amorphous silicon (a-3i:H) for its active layer.

In the figure, 31 is a glass substrate, 32 is approximately 1100n
a gate electrode made of chromium (Cr) having a thickness of 3;
3 is a gate insulating film made of silicon nitride (StN) with a thickness of about 300 nm, and 34 is a-3 with a thickness of about 50 r+m.
The i:H active layer is formed by a plasma CVD (chemical vapor deposition) method using a reactive gas based on silane (SiH4) gas.

35-1.35-2 is SiH, and phosphine (PH3)
Doping about 0.5% or active chemical vapor deposition (
The n′″a-3tsH layer (
36-1.36-2 is an electrode made of titanium (Ti) with a thickness of approximately 100nIII,
S and D are sources in which these two layers are stacked, respectively.
This is the drain electrode.

In the conventional TPT structure shown in FIG. 3 above, the gate 32
and the source and drain electrodes overlap at their ends.

Because of this structure, the gate insulating film 33 and a-S
i: When a pinhole occurs in the HIJ 34, there is a problem that the source electrode or drain electrode and the gate electrode are short-circuited with low resistance, that is, a low-resistance short-circuit condition occurs.

Such pinholes are likely to occur due to patterning residue during gate electrode formation, dust during insulating film formation, and the like, and it is extremely difficult to solve this problem.

FIG. 4 is a diagram for explaining the planar structure of a liquid crystal panel using a TPT matrix. As seen in the figure, drain pass lines D+, Dz . . . and gate pass lines G+, Gz . A large number of TPTs are connected.

(Problems to be Solved by the Invention) If the above-mentioned pinhole occurs in one of these TPTs and the gate electrode and the drain or source electrode are short-circuited, the gate pass line and the gate pass line to which that TPT is connected are Since the drain pass lines are shorted, all TPTs on these pass lines become inoperable, ie, line failure occurs.

Therefore, in order to solve this problem, the inventors of the present application proposed in Japanese Patent Application No. 161957/1982 that the gate electrode and the drain or source electrode are offset, and that the drain or source electrode is located on the surface of the active semiconductor layer in the offset region. We proposed a thin film transistor structure that does not cause line defects even if pinholes occur, by providing a structure with a derived low-resistance layer.

The principle of TPT is shown in FIG.

In the figure, 1 is a glass substrate, 2 is a gate electrode, 3 is a gate insulating film, 4 is an a-3t:H operation layer, 5-1.5-
2 is n''a-3i, 6-1 is an ITO transparent electrode (gate electrode D). The drain electrode made of ITO in 6-1 is arranged offset from the gate electrode, and the ITO electrode is placed in the offset region. An n''a-3i:8 layer 5-1 having a predetermined resistivity derived from directly below 6-1 extends.

With this configuration, even if a pinhole exists in the gate insulating film 3 or the like and a short circuit occurs between the n″a-3t:8 layer 5-1 and the gate electrode 2, the gap between the drain electrode and the gate electrode 2 In this structure, a resistor of an extension of the n″a-3t:8 layer 5-1 is inserted.

While the resistance value of the pass line is several tens of Ω, the resistance value of the extension of the n″a-3t:H layer 5-1 is IMΩ.
~ several tens of MΩ, so the gap between the pass line and gate electrode 2 is effectively equivalent to an open state, so the potential of the pass line is hardly affected, and therefore the TPT connected to the pass line will not be affected at all. Therefore, the presence of pinholes does not immediately cause line failures, unlike in the conventional case.

On the other hand, regarding the resistance when ON, the region of this n0 part can be made narrow to approximately 1 μm, so it is expressed as
The resistance is approximately 0.00Ω, and can be made into a resistance that does not affect the driving of liquid crystals and the like.

An object of the present invention is to provide a method for manufacturing a thin film transistor that can easily manufacture a TPT having the above-described offset structure.

[Means for solving problems]

In the present invention, the Ti layer shown in FIG.
A transparent electrode consisting of n'''a-
After fabricating a TPT with a conventional structure having a drain electrode (or source electrode) in a stacked structure with a 3tsH layer, a negative photoresist film is formed on a transparent insulating substrate including the drain and source electrode surfaces, and a gate electrode is formed. By exposing the photoresist film by irradiating parallel ultraviolet light obliquely from the back side of the substrate as a mask, a resist film having an offset with respect to the gate electrode is formed, and then using this resist film as a mask, the drain electrode or An end portion of the Ti layer above the source electrode is selectively removed. In this way, a drain or source electrode offset with respect to the gate electrode and a low resistance layer led out from the electrode are formed as shown in FIG.

[For production]

When exposure is performed by irradiating parallel ultraviolet light obliquely incident from the back side of the substrate, the gate electrode made of Cr does not transmit the ultraviolet light, but other layers other than this do not transmit the ultraviolet light.

That is, since the gate insulating film, the a-3i:8 layer, and the transparent electrode all transmit ultraviolet light, the negative photoresist film is formed in a pattern in which the light-shielded portions by the gate electrode are removed. Moreover, since the ultraviolet light is incident from a direction having a desired inclination angle with respect to the direction perpendicular to the substrate, the resist film is formed offset with respect to the gate electrode serving as a mask. Therefore, by selectively removing the transparent electrode using this as a mask, the drain (or source) electrode is formed offset from the gate electrode.

〔Example〕

FIG. 1 shows an embodiment of the present invention.

In the same figure (al indicates a TPT manufactured by a conventional manufacturing method. In the figure, 1 is a transparent insulating substrate such as a glass substrate, 2 is a gate electrode made of Cr with a thickness of approximately 1100 nm, and 3 is a gate electrode of approximately 300 nm. 4 is an a-3i film with a thickness of about 20 nm.
:H working layers, these are plasma CVD (P-CV
D) formed by a method.

5-1.5-2 is 5iH doped with about 0.1% PH3
n"a-3i (thickness approximately 80 nm) formed by P-CVD method using n as a reaction gas, 6-1.6
-2 is a transparent electrode made of ITO, S is a source electrode, and D
indicates the drain electrode.

As shown in the figure (b), a negative resist 7 is formed on top of this by a spin code method or the like, and then the figure [C
1, when this negative resist film 7 is exposed from the back side of the glass substrate 1 with parallel ultraviolet light 8 incident obliquely on the substrate, an unexposed area 9 is formed in the area masked by the gate electrode 2. occurs.

Next, this is subjected to a development process to remove the unexposed area 9, and as shown in FIG. 10 has an offset with respect to the gate electrode 2, but since it is self-aligned with the gate electrode 2, its position and shape can be determined with high precision.

Next, as shown in FIG. fQ), using the resist film 7' as a mask, a mixed solution of ferric chloride (FezCIs aqueous solution) and hydrochloric acid (50% HCI) is applied in the opening 10 of the ITO layer 6-1. The exposed end 11 is selectively removed. Since the above mixed solution does not remove the n"a-5i:H layer 5-1, the n"a-3i:H layer 5-1 is left inside the opening 10.
The end portion remains in the shape derived from directly below the ITO layer 6-1. The end of the n''a-3tsH layer 5-1 thus obtained is connected to the drain electrode and serves as the low resistance layer 12 disposed in the offset region.

Next, the resist film 7° is removed.

As described above, according to this embodiment, the gate electrode 2 and the ITO 156-
1 do not overlap with each other, and the low resistance layer 12 is formed in the offset HJ region on the active semiconductor layer 4, that is,
A TPT having a structure in which the gate electrode 2 and the drain (or source) electrode are offset is obtained. FIG. 3 shows a cross section of the main part of the TPT obtained in this example.

〔Effect of the invention〕

According to the present invention, even if there is a pinhole on the gate electrode, a TPT that does not cause a low resistance short circuit can be easily manufactured.

[Brief explanation of the drawing]

Fig. 1 is a sectional view of the main parts of an embodiment of the present invention showing the manufacturing process in order; Fig. 2 is a sectional view of the main parts of a completed TPT obtained by the above embodiment; Fig. 3 is a conventional TPT. FIG. 4 is an explanatory diagram of the planar structure of a conventional TPT. In the figure, 1 is a transparent insulating substrate, 2 is a gate electrode, and 3 is a transparent insulating substrate.
4 is a gate insulating film, 4 is an active semiconductor layer, 5-1.5-2 is an n"a-3i:H layer, 6-1. 6-2 is an ITO layer, 7
．． 7' is the resist film, 8 is the ultraviolet light, 9 is the unexposed area, 1
0 is an opening, 11 is an exposed end of a transparent electrode, 12 is a low resistance layer, S is a source electrode, and D is a drain electrode. ,i! BE -r, N (encouragiF41H 1st figure douiza [=January - tip' measurement 91 sun 3 lower F-cho's half place 8 games Akira Tatsugo 2nd figure Cb table/ITF lower r'r + shunsei Ton J! Specified Figure 3 Narrow Q TFT/l Plane Encyclopedia Tze9ba I Figure 4 Procedure First 11th Orthography (Spontaneous) Showa 6λ/February 2nd 1, yJ'r display [Ha061 Patent Application No. 222566 2, Name of the invention Method for manufacturing thin film transistors 3, '4 Relationship with the case of the person acting as a city administrator 522) FUJITSU LTD. 1 Back page 7, Subject of amendment (1) ``Claims j'' column of the specification (2) ``Detailed description of the invention'' column 8 of the specification, Contents of the amendment (1) The scope of claims in the specification of the present application is amended as shown in the attached sheet. (2) The detailed explanation column of the same invention is amended as follows. (a) Page 4, lines 5 to 5 of the same page. "Reactive chemical vapor deposition (RCVD)" in line 6 is corrected to "plasma chemical vapor deposition (PCVD)." (b) rTi layer J on page 8, line 9 of the same page. , rlT
o layer”. 9. List of Attached Documents (1) Amendment “Claims” 2. Claims A transparent insulating substrate (12) with a coating (2) and a gate insulating film (3) and a transparent electrode (5-1゜5-2) on which a semiconductor layer (4) having a predetermined conductivity type is formed.
are stacked to form a source electrode (S) corresponding to the gate electrode.
) and a drain electrode (D), a tan-shaped resist film (7) is formed on the entire curved surface of the base 1 including the surfaces of the source electrode and the drain electrode, and is incident on the back surface of the substrate at a predetermined inclination angle. By exposing the main left resist film to ultraviolet light (8) using the gate electrode as a mask, a resist Il'J (7') having an opening (10) offset with respect to the gate electrode is formed. and then selectively removing an end portion (11) of the transparent electrode layer of at least one of the source electrode or the drain electrode exposed in the opening (10) using the resist film (7°) as a mask. A method for manufacturing thin film transistors that focuses on

Claims (1)

[Claims] A gate electrode (2), a gate insulating film (3) on a transparent insulating substrate (12), an active semiconductor layer (4) having a predetermined conductivity type thereon, and a transparent electrode (5). -1, 5-2) to form a source electrode (S) and a drain electrode (D) corresponding to the gate electrode, and then a positive electrode is formed on the entire surface of the substrate including the surfaces of the source and drain electrodes. A type resist film (7) is formed, and the positive type resist film is exposed to ultraviolet light (8) incident on the back surface of the substrate at a predetermined angle using the gate electrode as a mask. A resist film (7') having an offset opening (10) is formed, and then the resist film (7') is used as a mask to open the opening (10).
10) selectively removing an end portion (11) of the transparent electrode layer of at least one of the source electrode or the drain electrode exposed in the thin film transistor.