JPS6376183A - Testing device for magnetic bubble memory - Google Patents

Abstract

PURPOSE:To decrease the necessary time of a central processing device action by storing the data into a second random access memory and detecting the defect of a minor loop when the defect detection is executed by a collating circuit. CONSTITUTION:A central processing device writes the writing data in parallel to a first RAM 16, and for the output, synchronized by a generator timing in an AND circuit and the output is written through a gate coil driver into a bubble memory. The data read from a bubble memory by the next timing are inputted through a sense amplifier to a defective loop detecting circuit. After the data are latched by a flip-flop, the collation with the written data is obtained at a collating circuit 18. When the collation is obtained for a minor loop and it is discovered that a defect is present, the contents are stored into a second RAM 17. When the central processing device reads the second RAM 17 at the subsequent suitable time, the presence and absence of the minor loop defect can be judged.

Description

[Detailed Description of the Invention] [Summary] As a device for testing the presence or absence of a defective minor loop when the capacity of a magnetic bubble memory is increased, the number of pages to be processed and the gate cycle can be arbitrarily set for the central processing unit.
Moreover, the present invention is a magnetic bubble memory testing device that stores the presence of a defective minor loop in a random access memory and processes it later.

[Industrial Field of Application] The present invention relates to a test device for checking whether or not there is a defect in the minor loop of a minor loop/major line type magnetic bubble memory.

In conventional magnetic bubble memory, the central processing unit was fully involved in detecting defective minor loops, so when the memory density increases, the required processing speed approaches the operating speed of the central processing unit, and the processing capacity decreases. Since there was a drawback that the product could not be used to its full potential, research was desired to find a solution.

[Prior Art] FIG. 3 is a block diagram showing a conventional test device. Third
In the figure, 1 is a defective loop detection circuit, 2 is a central processing unit, 3 is a minor loop/major line type bubble memory device, 4 is a timing generator, 5 is a gate coil driver, and 6 is a sense amplifier. Further, in the defective loop detection circuit 1, 11 is a central processing unit data bus;
12 is a write data shift register, 13 is a read shift register, 14 is an AND circuit, and 15 is a flip-flop. The shift registers 12 and 13 are both connected by a data bus 11 so that they can be accessed from the central processing unit 2. A defective minor loop is detected as a defect when an abnormality is detected when the data written from the central processing unit 2 is compared with the data read.

For this purpose, for example, 8-bit data is stored in parallel in the write data shift register 12, and each bit is serially sent out as a write pulse using a clock. At this time, synchronization is achieved in the AND circuit 14 using a pulse from the timing generator 4, and then the write driver is driven.

The data written in the bubble is read out at the next timing and once launched in the flip-flop 15. Next, the data is taken into the continuous data shift register 3 and converted into 8-bit parallel data. The 8-bit parallel data is then taken into the central processing unit and compared against previously written data.

As a result, when a mismatch is found in the data, it is determined that the minor loop is defective.

This defective marb detection device uses fixed values for the number of memory data and gate period for bubble memory drive.

[Problems to be Solved by the Invention] In the conventional circuit configuration shown in FIG. 3, only the processing time by the central processing unit required about 10 microseconds per bit. Therefore, when one byte is used for write data, it takes 80 microseconds to process just one byte, which is close to the limit of the central processing unit's ability.

Therefore, if this method were applied to a device with a larger memory capacity, the processing operation could no longer be adapted due to the capabilities of the central processing unit.

In addition, the number of memory pages and the gate period were only set fixedly by a predetermined program.

Therefore, only uniform mechanical processing could be performed during the test operations.

An object of the present invention is to improve the above-mentioned drawbacks, and to detect defective loops by a central processing unit, without performing a direct operation of matching and outputting the faulty loops, the central processing unit performs matching and detecting faults by hardware, and reads out the accumulated data. An object of the present invention is to provide a bubble memory testing device that efficiently performs processing in a central processing unit testing device.

[Means for Solving the Problems] FIG. 1 shows only the configuration of a defective loop detection circuit as the principle configuration of the present invention. In FIG. 1, 11 is a data bus with the central processing unit, 16 is a first random access memory (hereinafter, random access memory will be abbreviated as RAM), 17 is a second RAM, and 18 is a verification circuit. ing.

A magnetic bubble memory device (not shown) is
The present invention is a testing device for a magnetic bubble memory that detects a failure in a minor loop when the memory is of a major line type by writing data in the minor loop and processing the read output by a central processing unit, and the present invention has the following configuration.

That is, a first RAM 16 in which the data pattern is written;
It is provided with a second RAM 17 in which the contents are written when a defective pattern is confirmed, and a verification circuit 18 that performs verification between the output of the first RAM 15 and the read output of the bubble memory. In addition to the configuration of the first invention, the second invention has a configuration that allows the number of pages to be processed and the gate period to be set to predetermined values from a peripheral device (not shown) of the central processing unit.

[Operation] In FIG. 1, the central processing unit writes write data to
The data is written in AM16 in parallel, and its output is synchronized with the generator timing in an AND circuit and written into the bubble memory via the gate coil driver 5. The data read from the bubble memory at the next timing is input to the defective loop detection circuit via the sense amplifier. Then, after lunch at the printer buffer, the collation circuit 18 collates the data with the written data. When a defect is found by checking each minor loop, the contents are stored in the second RAM 17. If the central processing unit reads the second RAM 17 at a later appropriate time, it can determine whether there is a minor loop failure.

Next, the central processing unit can control the number of pages and gate period to predetermined values from the peripheral device according to the minor loop to be checked, so as to perform the most suitable operation.

The write and read terminals to the bubble can be connected in parallel to multiple chips.

[Embodiment] FIG. 2 shows, as an embodiment of the present invention, a case where the defective loop detection circuit of FIG. 1 is provided with a defective loop mask RAM to make processing more efficient. In Figure 2, 19 is the third
A defective loop mask/random access memory as a RAM is connected in parallel with the first RAM. Also, 20 is E
A verification circuit is configured with an OR circuit. When a defective loop within the chip is detected for the first time, there is no data to be stored in the third RAM 19, so the test is started as described above. When a defective loop is detected, it is preferable that the central processing unit records it in a recording device. Next, when detecting whether a defective loop has occurred in the same chip, data other than the data of the defective loop is stored in the third RAM 19 in advance.

That is, the data in the third RAM is the write data pattern RAM.
This is to prevent data No. 17 from being written. Therefore, regarding the data written by the third RAM, EO
If the R circuit 20 detects a mismatch, it will know that a new defective loop has been transferred, and will store it in the second RAM 17. By providing the third RAM 19, the second RA
The reliability of M17 data continues to increase.

Next, although a plurality of counters for page management are prepared under the control of the central processing unit, in the present invention, an external peripheral device is used to set the set values of these counters to predetermined values. Therefore, since the size of the page to be tested is not fixed, the test can be completed effectively in a short time.

[Effects of the Invention] Thus, according to the present invention, the interface with the bubble can be parallelized as a configuration of the defective loop detection circuit.
Also, since it controls the central processing unit,
Due to the detection of defective bubble chip loops, the time required for central processing unit operation can be reduced. In other words, the operation for detecting a defective loop can be performed at the same speed as the bubble operation, and is not related to the central processing unit capacity. It is possible to test large-capacity, high-speed bubble memory in the minimum amount of time. Furthermore, since the number of successive/write pages and gate period can be set to predetermined values, tests can be performed under various conditions, improving the reliability of test results.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of a conventional defective loop testing device. Knee: Defective loop detection circuit 2 - Central processing unit 3 - Bubble memory device 4 - Timing generator 5 - Gate coil driver 11 - Central processing unit data bus 16 - 1st RAM (for data pattern) 17 - 2nd R
AM (for defective pattern) 18-verification circuit 19--3rd RAM (for pattern mask) 20-EO
R circuit patent applicant Fujitsu Limited Agent Patent attorney Eisuke Suzuki Daimitsu Y Agency iida 1j Figure 2

Claims (1)

[Claims] I. A magnetic bubble memory testing device that detects defects in the minor loop by writing data in the minor loop of a magnetic bubble memory device and processing read output by a central processing unit, wherein at least a data pattern is written. A first random access memory (16) is used to store the defective loop, and a second random access memory (16) is used to write the contents when a defective loop is confirmed.
17) and a verification circuit (18) that performs verification between the output of the first random access memory (16) and the bubble memory readout output.
), when the verification circuit (18) detects a defect, the data is stored in the second random access memory (17);
A magnetic bubble memory testing device characterized in that the central processing unit detects a minor loop failure based on the read output of the second random access memory (17). II. In a magnetic bubble memory test device that detects defects in the minor loop by writing data in the minor loop of a magnetic bubble memory device and processing read output by a central processing unit, the first random access is performed by writing at least a data pattern. A memory (16) and a second random access memory (16) into which the contents are written when a defective loop is confirmed.
17) and a verification circuit (18) that performs verification between the output of the first random access memory (16) and the bubble memory readout output.
), the data when a defect is detected by the matching circuit (18) is stored in a second random access memory (17), and the central processing unit is configured to read out data from the second random access memory (17). 1. A testing device for a magnetic bubble memory, which detects a defect in a minor loop, and is characterized in that the central processing unit is capable of setting the number of pages and gate period to be processed from its peripheral devices to predetermined values.