JPS6375959A - Priority order decision circuit for serial type bus - Google Patents

Abstract

PURPOSE:To accelerate the decision of priority order, and to reduce the number of control signals on a bus, by providing a bus control signal setting panel, inputting the bus request signal of a bus master ranked higher than its own device, to the bus control signal setting panel in parallel, and detecting a bus grant signal in the inside. CONSTITUTION:Masters 10-1-10-n including bus request control circuits 1-n are provided, and in addition to those, bus control signal setting devices 11 are provided. In each of the bus control signal setting devices 11, the bus control signal setting panel 12 which sets the priority order of each master is provided, and receives the bus request (BSRQ) signal from each master, and decides the priority order. The bus grant (BGNT) signal is returned from the bus control signal setting device 11 in its own master to the master having the highest priority, to which the jurisdiction of the bus is attached. The priority of the master is decided by the bus control signal setting panel 12, and it is possible to change the priority order only by changing setting on the bus control signal setting panel 12.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Prior Art Problems to be Solved by the Invention Means for Solving the Problems Action Embodiments Effects of the Invention [Summary] On a common bus In the serial type bus priority determination circuit, a bus control signal setting panel is provided in all bus masters, and bus request signals of bus masters higher than the bus master are inputted in parallel to this bus control signal setting panel.
It internally detects bus grant number 6, speeds up priority determination, and reduces the number of control signals on the bus.

[Industrial application field]

The present invention relates to a bus priority determination circuit, and particularly to a serial bus priority determination circuit that determines the priority of each bus master to the bus when a large number of bus masters simultaneously access memory or Ilo on a common bus. Concerning decision circuits.

[Conventional technology]

When a large number of bus masters are connected on a common bus, if there are multiple accesses from the bus masters to the memory via the bus at the same time, the priority of this bus master is It is necessary to decide.

3 and 4 are examples of conventional priority order determination methods, with FIG. 3 showing a serial priority determination method and FIG. 4 showing a parallel priority determination method, respectively. In the figure, 1, 2, 3 to n indicate that bus masters (hereinafter referred to as masters) are connected. Each master handles bus requests. signal (hereinafter abbreviated as BSRQ) and a bus grant signal (hereinafter abbreviated as BGNT), and the BSRQ of the previous stage master and the BGNT of the next stage master are connected.Each master has a bus clock signal (hereinafter abbreviated as BCL).
(abbreviated as K) is input, and the control timing is determined thereby. In addition, a BUSY signal is issued from each master to inform the current usage status, and is input to each master.

In this serial prioritization scheme, the masters are ordered from the left, namely master 1 . Master 2゜... BSRQ is sent from the upper master 1 to the lower master n for each 0 bus clock whose priority is determined in the order of master n.
is output, and this is input as the BGNT signal of the lower master. For example, the BSRQ of master 1 is input as the BGNT signal of master n, bus usage is determined according to the priority of the masters, and the BUSY signal is issued from the master that is permitted to use the bus accordingly, and the bus usage of other buses is determined. prohibited. According to this serial type priority determination system, the bus use order can be determined with a small number of signal lines.

FIG. 4 shows another conventional example of a parallel priority order determination system. In the figure, 1, 2, 3. . . . n is a master, indicating that n masters are connected as in the case of FIG. 41 is a priority encoder, 42 is a decoder, and BSR of each master 1 to n.
The Q signal is input to a priority encoder 41, and the priority determined there is decoded by a decoder 42 and then returned to each master as a BGNT signal. At this time.

BGNT is returned only to the master with the highest priority among the masters that requested the bus at the same time, and the 0 control timing that has mastery of the bus is performed using BCLK.

The same is true for the serial type. In addition, a BUSY signal is issued from the master that has bus control to indicate that the bus is currently in use and cannot be used by other masters0. [Problems to be solved by the invention] Third In the case of the conventional serial priority determination method shown in the figure, the time it takes for master 1's BSRQ to be input as the BGNT signal of master n and determined is the maximum delay time until bus priority determination is p, and Determine the period. Now, the number of masters is n, and the delay time for 1 master is t
d.

The maximum delay time 'l' dI == n * t dl. As is clear from this, in the serial type prioritization scheme.

Since the delay time is proportional to the number of masters, there is a problem that it becomes impossible to speed up priority determination as the number of masters increases.

Furthermore, in the case of the parallel priority determination method shown in Fig. 4,
The time it takes to determine the bus priority is based on the BSRQ of each master.
The signal is determined by the time it takes for the signal to pass through the priority encoder 41 and decoder 42 and to be input as BGNT to each master.

Maximum delay time Td ==td, +td2 (encoder delay) +td, (decoder delay), which determines the period of BCLK. This T 4
Fi is constant regardless of the number of masters, and has the advantage of increasing speed even when the number of masters is increased, but when the number of masters is n, the number of control signals is 2n
The problem is that the number of control signals increases, and conversely, the number of other control signals on the bus is insufficient and the number of masters is limited.

In addition, in both types, the bus priority is determined in advance and configured on the device, but when a new master is added, the wiring on the bus is changed, or the master is replaced without replacing the master. There is a problem that the priority order cannot be changed freely in the serial method.However, in the case of the serial method, the priority order can be changed by replacing the master, but this is because other function boards including that master The condition is that it does not affect the connection to the bus, Ilo, etc. In reality, physical and electrical conditions are often not satisfied due to replacement.

The present invention has been made in view of these points,
Provided is a serial bus priority determination circuit that takes less time to determine priorities, requires less number of bus control signals, and can easily change priority settings without replacing bus wiring or masters. The purpose is to

[Failure to solve the problem]

FIG. 1 is a block diagram of the principle of this invention.

In the figure, 10-1.10-2. -10-n are masters including bus request control circuits 1-n, respectively, and each has a bus control signal setting device 11 in addition to the masters. Each bus control signal setting device 11 is provided with a bus control signal setting board 2 for setting the priority order of each master.

It receives the BS'RQ signal from each master and determines the priority order. The BGNT signal is returned to the master with the highest priority from the bus control signal setting device 11 in the own master, and
This master will have control of the bus. When the bus is in use, a BUSY signal is issued, so the use of the bus at this time is prohibited.

The priority of the master is determined by the bus control signal setting board 12, and the change can be made by this bus control signal setting board 12.
[Operation] The BGNT signal to each master 1 to n is returned from the bus priority setting device within its own bus master, so the only control signal on the bus is BSRQ. Tona Jino < 1/2 of Larel method
becomes.

Further, the bus delay time is equivalent to one master stage, and can be significantly reduced compared to '/n of the conventional serial system.

〔Example〕

FIG. 2 shows an embodiment of this invention. In FIG. 2, the same members as in FIG. 1 are given the same numbers.

The masters 10-1 to 10-n each include bus request control circuits 1 to n and a bus control signal setting board 12,
2 analogues) 22.23 and 1 inverter 2
The bus control signal setting device comprises four bus control signal setting devices. AND gate 23 is a high-level bus request/bus busy detection gate (hereinafter referred to as 23
(called the high-level bus request/bus busy detection gate)
The output of the bus control signal setting board 12 and the BUSY signal, which will be described in detail later, are input to the input.

The bus control signal setting panel 12 is as shown in FIG.

(n-1) terminal rows a1~a□, b1~ arranged in two rows
It is a board with br1-1, and one terminal a1-an
-x are connected in parallel to the terminals a1 to aml of the corresponding bus control signal setting boards 12 of the other bus masters 101 to 10,1, respectively. The other terminals ~bn-t are the high-level bus request-bus busy detection gate 2 as described above.
Connected to 3. 1st priority pass master 10-1
The bus control signal setting panel 12 of
Terminals on the bus busy detection gate 23 side ~b...
All are considered to be at the rHJ level.

Further, the bus request signal B8RQ from the bus request control circuit 1 is connected to the top terminal a via the inverter 24 as *B8RQ.

(The signal at this terminal is assumed to be the bus sending bus request signal *B8RQ1 of master 1.) As a result, the BSRQs of each bus master are connected in parallel.

In the bus control signal setting board 12 of the second priority bus master 10-2, as shown in Figure 2, connect the output of the input terminal 24 to the second terminal a, and connect the terminal a1 to the terminal b1. Then, set the terminal excluding the terminal ``H'' to brl-1.
Apply the level.

Thereafter, the bus control signal setting board 12 is similarly set according to the priority order of the master. In the last n-th bus control signal setting board 12, terminals a1 to a, and terminals b8 to b
The 0 AND gate 22 to which n-i is connected has one input of the BSRQ from the bus request control circuits 1 to n, and the high-level bus request -
The output from the bus busy detection gate 23 is used as the other input, and it operates as a bus grant detection gate (hereinafter referred to as bus grant detection gate 22) that detects whether permission to use the bus has been granted.

Reference numeral 24 is the already mentioned inverter, which inverts the output from the pass second detection gate 22 and connects it to the terminal al of the bus control signal setting board 12 which has a lower priority than the self and the self.
'=an-1. Further, the output of the high-level bus grant detection gate 22 is returned to each bus request control circuit 1 to n itself as BGNT. This is acting as a bus request buffer.

The operation of the serial type bus priority determining circuit configured as described above is as follows.

Now, when the bus is not being used by any master, *BUSY is set to rHJ level.

Focusing on the first priority bus master 10-1.

All terminals b1 to b7-3 of the bus control signal setting board 12 are r
It's HJ, and *BU8Y is also rHJ.

The output of the high-level path request Φ bus busy detection gate 23 is "H". Therefore, at this time, if BSRQ is issued from the bus request control circuit 1.

The bus grant detection gate 22 turns on and outputs "HJ. This rHJ level is returned to the bus request control circuit 1 as a BGNT signal, and in response to this, the bus request control circuit 1 establishes bus control and controls the bus. Performs operations such as sending signals.

The output of the bus grant detection gate 22 is connected to the inverter 24
This signal *B S RQl is connected to the terminal a1 of the bus control signal setting board 12 of the second priority bus master 10-2 and below. will be connected and therefore the second
There is at least one rLJ input to the high-order bus request/bus busy detection gate 23 of the bus master below the priority level, and the output of the gate 23 becomes rLJ,
The bus grant detection gate 22 becomes rLJ. Therefore, the BGNT of rLJ is not returned to the bus request control circuits below the second priority level, and the use of the bus is prohibited. Furthermore, when one of the masters 1 to n occupies the bus, BUSY becomes rHJ and *BUSY input to the gate 23 becomes rLJ, preventing other masters from accessing the bus.

The bus master 10-2 with the second priority is selected after all from the bus master 10-1 with the first priority.
B8RQ1 is not input.

And *BU8Y is 0, which is only when input is not input.Similarly, the master 3 with the third priority j@ is selected when the bus master 10- with the first priority and the second priority is selected.
1.10-2 are not selected, and *
This happens when there is no BU8Y.

As described above, the terminals a1 to a of the bus control signal setting board 12
Depending on the connection status of n-, and terminal -w bn-,
The priority of that bus master is determined, so it's the other way around.

It is clear that by changing this connection state, the priority order of the bus masters can be changed very easily.

It goes without saying that the operations described above are performed in accordance with the clock BCLKK.

[Effects of the Invention] As described above, in this invention, since the bus request signal (BSRQ) higher than itself is inputted to each path master in parallel, the delay time of this signal can be reduced by one master stage. This becomes 1/IN of the conventional serial system, making it possible to speed up the bus priority determination time. Also BGNT
The control signals on the bus are because the signals are detected inside the bus and star.

It is possible to reduce Sibus control signals such as BSRQ only.

Furthermore, the bus priority order can be changed very easily by simply changing the terminal connections on the bus control signal setting panel.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of the invention. FIG. 2 is a diagram showing one embodiment of the present invention. FIGS. 3 and 4 are diagrams showing conventional examples. 1 to n... Bus request control circuit. 10-1 to 10-n... Bath rxter. 11... Bus control signal setting device. 12...Bus control signal setting panel. 22...Bass grant detection gate. 23...High-level bus request/bus busy detection gate. 24...Inverter.

Claims (1)

[Claims] In the serial type bus priority determination circuit, each bus master includes a bus control signal setting board (12), a high-level bus request/bus busy detection gate means (23), and a bus grant detection gate means (22). ), and an inverter (24), which inputs in parallel a signal requested by a bus master higher than itself to the bus control signal setting board (12), and transmits a bus grant signal to the bus grant detection gate means (22). A serial type bus priority determination circuit characterized by detecting