JP2714163B2 - Bus control method - Google Patents

Description

Description: Object of the Invention (Industrial Application Field) The present invention relates to a system having a plurality of devices sharing a bus, and more particularly to arbitration (arbitration) relating to bus contention between devices. The present invention relates to a bus control system for performing.

(Prior Art) In a system in which a plurality of devices are interconnected by a bus, a plurality of devices simultaneously request a bus acquisition (bus use request).
, It is necessary to arbitrate which device uses the bus. Conventionally, the following arbitration method has been generally used. That is, a fixed priority is given to each device (generally, the priority of the device is determined by the mounting slot position in the chassis), and when a plurality of devices issue requests at the same time, the highest priority among them is given. This is a method in which expensive devices can acquire a bus. However, this method has a drawback that if a high-priority device issues a bus acquisition request one after another, a low-priority device cannot acquire a bus for a long period of time.

In order to solve the above-mentioned drawbacks, a bus arbitration method has been proposed in which a concept of a bus acquisition privilege request is introduced in addition to a normal bus acquisition request. In this method, one new bus acquisition privilege request signal line is prepared, and each device is connected by wired-OR (Wired-OR) by the signal line. If the bus cannot be acquired for a certain period (Tk) despite the output of the bus acquisition request signal,
The device in turn outputs a bus acquisition privilege request signal. When this bus acquisition privilege request signal is output, the other devices that have not output the bus acquisition privilege request signal stop outputting this bus acquisition request signal if they themselves output the bus acquisition request signal. And cancels the bus acquisition request. As a result, the device that has output the bus acquisition privilege request signal can acquire the bus.

In the bus arbitration system using the bus acquisition privilege request (bus control by the privilege request system), at least the period
Since the bus can be acquired once during Tk, there is no possibility that the bus cannot be acquired forever. However, the opportunity to acquire a bus still causes imbalance between devices. For example, in a system in which a plurality of devices are interconnected by a clock synchronous control bus,
When set to 16T (T is a clock cycle), if two devices issue a bus acquisition request continuously (every cycle), the low-priority device can acquire only 1T bus during 16T, Priority devices are all the rest, ie 1 during 16T
5T can get a bus.

(Problems to be Solved by the Invention) As described above, in the conventional method in which the priority of the bus acquisition is fixedly assigned to each device sharing the bus, even if the device has a low priority, the bus is acquired by the bus acquisition privilege request. Even if a possible privilege request method is applied, there is a problem that the opportunity of acquiring a bus by a low-priority device is significantly less than that of a high-priority device.

Therefore, the problem to be solved by the present invention is to enable each of the devices sharing the bus to obtain the bus fairly in a system in which the priority of acquiring the bus is predetermined.

[Configuration of the Invention] (Means for Solving the Problems) The present invention provides a plurality of devices that share a bus of a clock synchronous control and have a predetermined priority regarding bus acquisition. Means for outputting a bus acquisition request signal, and a first state to a second state when a bus cannot be acquired even when the bus acquisition request signal is output and a bus acquisition privilege request signal is not output from another device. State holding means for returning to the first state when the bus can be acquired;
A means for outputting a bus acquisition privilege request signal when the state holding means is in the second state and the access request destination apparatus is not in a busy state; a state in which the access request destination apparatus is in a busy state; Means for inhibiting the output of the bus acquisition request signal when the bus acquisition privilege request signal is output from the other device in the first state; If there is no device that has output the acquisition request signal and has output the bus acquisition privilege request signal, the bus is set only when the bus acquisition request signal is not output from a device having a higher priority than the own device. If the own device outputs a bus acquisition request signal and there is a device that outputs the bus acquisition privilege request signal, the own device outputs the bus acquisition privilege request signal and It is characterized in obtaining a viewing bus when the bus acquisition privilege request signal from the high priority device from location is not output.

(Operation) According to the above configuration, if each device sharing the bus cannot acquire the bus even if it issues the bus acquisition request, the bus acquisition privilege request is not issued from another device and the access request destination device is not. If it is not busy, a bus acquisition privilege request is output by the transition from the first state to the second state of the state holding means. In this bus acquisition privilege request output state, the bus acquisition privilege If the request has not been output, it is possible to acquire the bus and access the access request destination device. When the bus can be acquired by the bus acquisition privilege request, the state holding unit returns to the first state, and the output of the bus acquisition privilege request stops. As a result, if there are devices that are still in the bus acquisition privilege request output state, the bus is acquired in order from the device with the highest priority among these devices. During this time, that is, while at least one device is in the bus acquisition privilege request output state, a device that newly acquires a bus cannot issue a bus acquisition request. Therefore, a low-priority device can share a bus as well as a high-priority device.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a system to which the present invention is applied. In the figure, reference numeral 11 denotes a bus of a clock synchronous control, and 12A, 12B, 12C and 12D are devices interconnected by a bus 11 and sharing the bus 11. Bus 11
Are accessed by devices 12A-12D (devices 12A
The main memory device MM and the shared memory device SM, which are the access request destinations of ~ 12D, are connected. In the system of FIG. 1, the priorities of the devices 12A to 12D regarding the bus acquisition are as follows.
It is assumed that the device 12A is the highest, and the device 12B, the device 12C, and the device 12D are in the following order. ▲ ▼ indicates device 12A ~
12D bus acquisition request signal output, ▲ ▼ indicates device 12A ~
12D bus acquisition privilege request signal input / output, true at low level. ▲ ▼, ▲ ▼, ▲
▼ indicates a bus acquisition request signal of the devices 12A to 12D (▲
▼) input, true at low level. ▲ ▼
Indicates that the device whose bus priority is one higher than its own device,
▼ from two higher devices, and ▲
▼ is a bus acquisition request signal input from three higher-level devices. Here, when there is no high-priority device corresponding to ▼ (i = 1 to 3), ▼ is fixedly set to false (high level). Also ▲
▼ indicates main memory MM, ▲ ▼ indicates shared memory
Each of the SMs is a busy signal (a signal indicating that an access request cannot be accepted).

13 is a bus acquisition request signal from the device 12A (▲ ▼)
Is a bus acquisition request signal line for transmitting data to the devices 12B to 12D (inputs of ▲ ▼ to ▲ ▼).
The bus acquisition request signal (▲ ▼) from B is sent to devices 12C and 12D.
(15), a bus acquisition request signal line for transmitting to (15) a bus acquisition request signal (▲ ▼) from the device 12C to the device 12D (O ▲ ▼)
Is a bus acquisition request signal line for transmitting to the bus. 16 is equipment
▲ ▼ to ▲ ▼ input of 12A, ▲ ▼, ▲ ▼ input of device 12B, and device 12C
Reference numeral 17 denotes a bus acquisition privilege request signal line used for transmitting a bus acquisition privilege request signal ▲ ▼ between the devices 12A to 12D. Outputs of the devices 12A to 12D are open collector outputs and are wired-ORed by a signal line 17. The signal lines 13 to 17 are pulled up by a power supply voltage + V via a pull-up resistor R. 18 is a busy signal from the main memory device MM ▲
Busy notification signal line for transmitting ▼ to the devices 12A to 12D, and 19 is a busy signal from the shared memory device SM.
This is a busy notification signal line for transmitting ▼ to the devices 12A to 12D.

The devices 12A to 12D in FIG. 1 have, for example, a bus acquisition control circuit of the same configuration for performing control (bus arbitration) regarding acquisition of the bus 11 among the devices 12A to 12D. FIG. 2 shows the configuration of the bus acquisition control circuit. In the figure, 21 is ▲
Each input from ▼ to ▲ ▼ is false (high level)
In this case, a bus acquisition request signal 32 (true at high level) indicating that a bus acquisition request state has occurred in its own device is detected, and a bus acquisition permission signal 32 indicating that bus acquisition is possible is performed.
An AND gate 22 for outputting (true at high level) 22 is false at the signal 33 (true at low level) indicating that the bus acquisition privilege request signal ▲ ▼ is output from any device except the own device. In this case, this is a NAND gate for detecting that the bus acquisition request status signal 31 is true and outputting a valid (low level) bus acquisition request signal ▲ ▼. Reference numeral 23 denotes an inverter for inverting the level of the bus acquisition permission signal 32, and reference numeral 24 denotes an AND gate for detecting that the signal 31 is true and the signals 32 and 33 are false.

Reference numeral 25 denotes a JK flip-flop for requesting a bus acquisition privilege (hereinafter referred to as a bus acquisition privilege request F / F, which has a J input for the output signal of the AND gate 24, a K input for the bus acquisition permission signal 32, and a clock input for the bus clock signal CLK. 26, a Q output signal of the bus acquisition privilege request F / F 25 and a bus acquisition request status signal 3
1 is an open collector output NAND gate that detects that both are high level and outputs a valid (low level) bus acquisition privilege request signal ▼. The output of the NAND gate 26 is connected to the input and output of its own device. 27 is an inverter for inverting the level of the input / output signal state, 28 is that both the output signal of the inverter 27 and the output signal of the bus acquisition privilege request F / F25 are at a high level, that is, A NAND gate 29 detects that the bus acquisition privilege request signal ▲ ▼ is output from the device and outputs a valid (low level) signal 33, and 29 is an AND gate. An AND OR gate 29 has an access request signal (hereinafter referred to as MM) indicating that an access request to the main memory device MM has been generated in its own device.
AND gate to which a busy signal ▲ ▼ from the main memory device MM is supplied.
29-1; an access request signal (hereinafter, referred to as an SM access request signal) 35 indicating that an access request to the shared memory device SM has occurred in the own device;
The AND gate 29-2 supplied with the busy signal ▲ ▼ from the SM and the output signals of the AND gates 29-1 and 29-2 are
OR gate 29 that performs OR operation and outputs bus acquisition request status signal 31
-3.

Next, the operation of the embodiment of the present invention will be described with reference to the timing chart of FIG. 3 in a case where a bus acquisition request is simultaneously and continuously generated in all the devices 12A to 12D shared by the bus 11. Will be explained.

First, it is assumed that in the cycle T1, an access request to the main memory device MM or the shared memory device SM occurs in the devices 12A to 12D, and the MM access request signal 34 or the SM access request signal 35 becomes true (high level). . At this time,
The main memory device MM and the shared memory device SM are not busy, so the busy signal on the busy notification signal line 18
▼ and busy signal on busy notification signal line 19 ▲
▼ is assumed to be false (high level).

The AND gate 29-1 in the AND OR gate 29 provided in the bus acquisition control circuit shown in FIG. 2 of each of the devices 12A to 12D has a busy signal when the MM access request signal 34 is true.
A high level signal is output only when ▼ is false.
And gate 29-2 in AND gate 29 is SM
A high level signal is output only when the access request signal 35 is true and the busy signal ▲ ▼ is false. The OR gate 29-3 in the AND gate 29 is the AND gate 29-1, 29.
The two output signals of -2 are ORed, and a bus acquisition request state signal 31 is output. Therefore, in the cycle T1, the AND control of the bus acquisition control circuits of all the devices 12A to 12D is performed.
OR gate 29 (of which OR gate 29-3) outputs a high level (ie, valid) bus request status signal 31. At this time, assuming that none of the devices 12A to 12D is in the bus acquisition privilege request state, the bus acquisition privilege request signal ▲ on the signal line 17 is at a high level (false), and thus the bus acquisition of the devices 12A to 12D is performed. The output signal 33 of the NAND gate 28 in the control circuit is also at a high level. In addition, NAND gate
28, the bus acquisition privilege request F / F 25 is in the reset state (that is, the own device is not in the bus acquisition privilege request state), and the bus acquisition privilege request signal on the signal line 17
Only when ▼ is low (true), that is, when any device except the own device is in the bus acquisition privilege request state and the bus acquisition privilege request signal ▲ ▼ is low, Become. Output signal 33 of NAND gate 28
Is supplied to the NAND gate 22 together with the bus acquisition request status signal 31. The NAND gate 22 outputs a low (valid) bus acquisition request signal only when both the bus acquisition request status signal 31 and the output signal of the NAND gate 28 are at a high level.
Output ▼. Therefore, in this embodiment, the cycle T1
, The low level bus acquisition request signal ▲ ▼ from the NAND gate 22 in the bus control circuit of all the devices 12A to 12D
Is output.

The bus acquisition request signal ▲ ▼ from the device 12A is output from the ▲ ▼ input of the device 12B, the ▲ ▼ input of the device 12C and the ▲
The signals are transmitted to the inputs via the bus acquisition request signal lines 13, respectively. Also, a bus acquisition request signal from the device 12B
▼ indicates a lower priority device 12C than the same device 12B.
The ▼ input and the ▲ ▼ input of the device 12D are transmitted via the bus acquisition request signal line 14, respectively, and the bus acquisition request signal ▲ ▼ from the device 12C is applied to the ▲ ▼ input of the device 12D having a lower priority than the device 12C. It is transmitted via the bus acquisition request signal line 15. In addition, ▲ of device 12A
Each input of ▼ ~ ▲ ▼, ▲ of device 12B
▼, ▲ ▼ input and ▲ of device 12C
The input is fixedly set to a high level (a state indicating that there is no input of the bus acquisition request signal ▼) by the signal line 16. The inputs of the AND gate 21 in the bus control circuits of the devices 12A to 12D are all
The inputs ▼ to ▲ ▼ and the bus acquisition request status signal 31 are connected. Andgate 21 is ▲
High level (valid) only when all of the inputs ▼ to ▲ ▼ and the bus acquisition request status signal 31 are high level
The bus acquisition permission signal 32 is output. Therefore, the cycle
At T1, a high-level bus acquisition permission signal 32 is output only from the AND gate 21 of the device 12A having the highest priority among the devices 12A to 12D, and the device 12A acquires the bus 11. On the other hand, the bus acquisition permission signal 32 from the AND gate 21 of the devices 12B to 12D having lower priority than the device 12A remains at a low level, and the devices 12B to 12D cannot acquire the bus 11.

Now, the bus acquisition permission signal 32 from the AND gate 21 has its level inverted by the inverter 23 and
Supplied to The AND gate 24 is also supplied with a bus acquisition request state signal 31 and an output signal 33 of the NAND gate 28. In the devices 12B to 12D that could not acquire the bus 11 in the cycle T1, the bus acquisition permission signal 32 from the AND gate 21 is at the low level as described above. In this case, the device
The output signals of the AND gates 24 of 12B to 12D become high level because the signals 31 and 33 are high level. And gate
When the 24 output signal goes high, the bus acquisition privilege request F /
The J input of F25 becomes high level, and the bus acquisition privilege request F / F25 is set at the start of the next cycle T2. That is, in the bus acquisition privilege request F / F25, the own device is in the bus acquisition request state (the bus acquisition request state signal 31 is at a high level) and the bus 11 cannot be acquired (the bus acquisition permission signal 32 is at a low level);
In addition, it is set when a device other than the own device does not output a valid bus acquisition privilege request signal ▲ ▼ (the output signal 33 of the NAND gate 28 is at a high level). When the bus acquisition privilege request F / F25 is set, when the bus acquisition request status signal 31 is at a high level, a low-level (valid) bus acquisition privilege request signal ▲ ▼ is output from the open gate output NAND gate 26. You. Therefore, in the present embodiment, the devices 12B to 1B that could not acquire the bus 11 in the cycle T1
The 2D bus acquisition privilege request F / F25 is set in the next cycle T2, and a low-level bus acquisition privilege request ▼ is output to the bus acquisition privilege request signal line 17. This allows
The bus acquisition privilege request signal line 17 goes low. Even if the bus acquisition privilege request F / F25 is set, if the access request destination device (the main memory device MM or the shared memory device SM to be accessed) is in a busy state, the bus acquisition request status signal 31 is AND-ed. False (low level) by OR gate 29
, The valid bus acquisition privilege request signal ▲ ▼ is not output from the NAND gate 26.

When the bus acquisition privilege request signal line 17 (signal ▼) goes low in cycle T2, the device 12A to 12D has a bus acquisition privilege request F / F25 that is not in the set state (ie, is not in the bus acquisition privilege request state). 3.) The output signal 33 of the NAND gate 28 of the device 12A goes low. In the device 12A, when the signal 33 goes low as described above, the bus acquisition request signal ▼, which is the output of the NAND gate 22, goes high (false). That is, in cycle T1, bus 11
The device 12A which has been able to acquire the bus acquisition privilege request signal (low level) from any device except its own device in the next cycle T2 even in the bus acquisition request state
When ▼ is output, a valid bus acquisition request signal ▲ ▼
Stop output of As a result, in cycle T2,
Among the devices 12B to 12C in the output state of the valid bus acquisition request signal ▲ ▼, the valid bus acquisition permission signal 32 only from the AND gate 21 of the device 12B having the highest priority, that is, the device 12B having the next highest priority after the device 12A. Is output, and the device 12B acquires the bus 11.

In the cycle T2, the device 12A cannot acquire the bus 11 because the output of the bus acquisition request signal 取得 is stopped, and the bus acquisition permission signal 32 in the device 12A is false. However, in cycle T2, a valid bus acquisition privilege request signal from another device (here, devices 12B to 12D)
Since ▼ is output and the own device (device 12A) is not in ▲ ▼ output state, the output signal 33 of the NAND gate 28 of device 12A does not become high level, and therefore, the bus acquisition privilege request F / F25 of device 12A. Is not set in the next cycle T3. In other words, if the device 12A that was able to acquire the bus 11 in cycle T1 is a device in the bus acquisition privilege request state among other devices in the next cycle T2,
Even if the bus 11 cannot be acquired in the same cycle T2, the bus acquisition privilege cannot be changed in the next cycle T3.

The bus acquisition privilege request F / F25 of the device 12B that has acquired the bus 11 in the cycle T2 is reset in the next cycle T3 by a valid bus acquisition permission signal 32 from the AND gate 21 of the device 12B. Therefore, in cycle T3, devices 12A,
This means that the bus acquisition privilege request F / F25 of 12B has been reset. On the other hand, the bus acquisition privilege request F / F25 of the devices 12C and 12D is still set, and the bus acquisition privilege request signal line
State 17 (▲ ▼) remains at the low level. In this case (in cycle T3), the output signal 33 of the NAND gate 28 of the devices 12A, 12B does not go high, and
12A and 12B (the NAND gate 22 thereof) cannot output a valid bus acquisition request signal ▲ ▼. Therefore, in the cycle T3, the devices 12C and 12 outputting the valid bus acquisition request signal ▲ ▼ (in the bus acquisition privilege request state)
The valid bus acquisition permission signal 32 is output from the AND gate 21 of the device 12C having the higher priority among the devices D, and the device 12C acquires the bus 11.

The bus acquisition privilege request F / F25 of the device 12C that has acquired the bus 11 in the cycle T3 is reset in the next cycle T4 by a valid bus acquisition permission signal 32 from the AND gate 21 of the device 12C. Therefore, in cycle T4, device 12A
This means that the bus acquisition privilege request F / F25 of ~ 12C has been reset. On the other hand, the bus acquisition privilege request F / F25 of the device 12D is still set, and the bus acquisition privilege request signal line 17
State (▲ ▼) remains at the low level. In this case (in cycle T4), the NAND gates of devices 12A-12C
The output signal 33 of 28 does not go high and therefore the device 12
A to 12C (the NAND gate 22 thereof) cannot output a valid bus acquisition request signal ▲ ▼. Therefore, in cycle T4, a valid bus acquisition permission signal 32 is output from the AND gate 21 of the only device 12D that outputs a valid bus acquisition request signal REQ (in the bus acquisition privilege request state),
The device 12D acquires the bus 11.

The bus acquisition privilege request F / F25 of the device 12D that has acquired the bus 11 in the cycle T4 is reset in the next cycle T5 by a valid bus acquisition permission signal 32 from the AND gate 21 of the device 12D. Therefore, in cycle T5, all devices 12
This means that the bus acquisition privilege request F / F 25 of A to 12D has been reset, and the state of the bus acquisition privilege request signal line 17 (the bus acquisition privilege request signal ▼) becomes high (false). That is, in cycle T5, there is no device that outputs a valid signal ▼. In this case, all devices 12A-1
In 2D, the output signal 33 of the NAND gate 28 becomes high level, and accordingly, the bus acquisition request signal ▼ which is the output signal of the NAND gate 22 becomes low level (true). That is, in the cycle T5, if the access request destination device is not busy, all the devices 12A to 12D again output a valid bus acquisition request signal ▼. Here, similarly to the case of the cycle T1, the device 12A having the highest priority among the devices 12A to 12D
A gets bus 11. Hereinafter, the device 12A ~
12D acquires the bus 11 in order.

Next, regarding the bus control (bus acquisition control) when the access request destination device is busy, the device 12A tries to continuously access the shared memory device SM, and the device 12B
Will be described with reference to the timing chart of FIG. 4 in a case where the main memory device MM is used for continuous access.

First, in the cycle T2, an access request to the shared memory device SM is generated in the device 12A, the SM access request signal 35 becomes true (high level), and the main memory device M
An access request to M occurs and the MM access request signal 3
Assume that 4 is true (high level). This cycle T
In 2, neither the main memory device MM nor the shared memory device SM is busy, so the busy signal ▲
It is assumed that both ▼ and busy signal ▲ ▼ are false (high level). Also, the bus acquisition privilege request signal ▲
▼ is also false (high level).

In the cycle T2, in the bus acquisition control circuit of the device 12A, the SM access request signal 35 is true, and the busy signal
Since ▼ is false, a valid bus acquisition request status signal 31 is output from the AND OR gate 29, and since the bus acquisition privilege request signal ▲ ▼ is false (the output signal 33 of the NAND gate 28 is To become)
Valid bus acquisition request signal from NAND gate 22
Is output. Similarly, in the bus acquisition control circuit of the device 12B, the MM access request signal 34 is true and the busy signal
Since ▼ is false, a valid bus acquisition request status signal 31 is output from the AND OR gate 29, and since the bus acquisition privilege request signal ▲ ▼ is false, a valid bus acquisition request signal ▲ ▼ from the NAND gate 22 Is output. When a valid bus acquisition request signal ▲ ▼ is output from the device 12A or 12B among the devices 12A to 12D, the cycle T2 in which the bus acquisition privilege request signal ▲ ▼ is false
, The high-level bus acquisition permission signal 32 only from the AND gate 21 of the higher priority device 12A of the devices 12A and 12B.
Is output, and the device 12A acquires the bus 11. In contrast, the bus acquisition permission signal 32 from the AND gate 21 of the device 12B having a lower priority than the device 12A remains at a low level, and
12B cannot get bus 11. In this case, the bus acquisition privilege request F / F25 in the bus acquisition control circuit of the device 12B is set at the start of the next cycle T3.

In the cycle T3, it is assumed that the main memory device MM is in a busy state, and the busy signal ▼ from the device MM is true (low level). Busy signal ▲ ▼
Is true, in the device 12B, the bus acquisition request status signal 31 is set to false by the AND gate 29 even if the MM access request signal 34 is true. Therefore, in the device 12B, even if the bus acquisition privilege request F / F25 is set, a valid bus acquisition privilege request signal
▼ is not output. In this case, in the device 12A, the output signal 33 of the NAND gate 28 maintains the high level state, so that the output of the bus acquisition request signal ▲ ▼ is not suppressed, and the cycle T3
Also, the device 12A acquires the bus 11.

In the next cycle T4, the main memory device MM enters the ready state, and the busy signal ▲ ▼ is false (high level).
It is assumed that In this case, a valid (low-level) bus acquisition privilege request signal ▼ is output from the NAND gate 26 of the bus acquisition control circuit of the device 12B, and the output of the bus acquisition request signal ▼ in the device 12A is suppressed. As a result, the device 12B acquires the bus 11.

Now, in cycles T5 to T7, the shared memory device SM
Is busy, and the busy signal from the device SM
It is assumed that ▼ is true (low level). In this case, in the device 12A, even if the SM access request signal 35 is true, the bus acquisition request status signal 31 is set to false, and the output of the bus acquisition request signal ▲ ▼ is suppressed. Therefore, in cycles T5 to T7, the device 12B continuously acquires the bus 11.

In the next cycle T8, it is assumed that the shared memory device SM is ready, and the busy signal ▼ is false (high level). In this case, in the device 12A, the bus acquisition request state signal 31 becomes true (high level), and the valid bus acquisition request signal ▼ is output from the NAND gate 22 again. Accordingly, in the cycle T8, the device 12A having the higher priority among the devices 12A and 12B that have output the bus acquisition request signal ▼ acquires the bus 11. On the other hand, in the device 12B that could not acquire the bus 11, the NAND gate 2 set by the bus acquisition privilege request F / F25 at the start of the cycle T9.
6 outputs a valid bus acquisition privilege request signal ▲ ▼. As a result, the bus acquisition request signal from the device 12A
The output of ▼ is suppressed, and in the cycle T9, the device 12B acquires the bus 11 this time.

Although the case where four devices share the bus 11 has been described above, the present invention can be applied to a case where five or more devices are used, or two or three devices.

[Effects of the Invention] As described in detail above, according to the present invention, if a device that shares a bus cannot acquire a bus even if it issues a bus acquisition request, a bus acquisition privilege request is not issued from another device. In addition, if the access request destination device is not busy, a bus acquisition privilege request can be immediately issued to suppress the output of a new bus acquisition request from another device. You can always get a bus in priority order. The high-priority device that could get the bus first
As long as there is a device in the bus acquisition privilege request output state, a new bus acquisition request cannot be issued (therefore, a bus acquisition privilege request cannot be issued), so that a low-priority device is equal to a high-priority device. You can share the bus. Further, according to the present invention, each device independently suppresses the output of the bus acquisition request and the bus acquisition privilege request according to the busy state of the access request destination device, so that efficient bus arbitration can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a system to which the present invention is applied. FIG. 2 is a diagram showing a configuration of a bus acquisition control circuit of the devices 12A to 12D in FIG. 1, and FIGS. Is a timing chart for explaining the operation. 11 ... bus, 12A to 12D ... device, 13 to 15 ... bus acquisition request signal line, 17 ... bus acquisition privilege request signal line, 18, 19 ...
Busy notification signal line, 21, 24, 29-1, 29-2 ... AND gate, 22 ... NAND gate (bus acquisition request signal output means), 25 ... bus acquisition privilege request F / F (state holding means), Two
6 NAND gate (bus acquisition privilege request signal output means), 28 NAND gate (suppression means), 29 AND-OR gate (suppression means), MM main memory device, SM
... shared memory device.

Claims (1)

(57) [Claims] In a system provided with a plurality of devices sharing a bus of clock synchronous control and having a predetermined priority regarding acquisition of the bus, a system for requesting each device to acquire the bus is provided. A bus acquisition request signal output unit that outputs a bus acquisition request signal; and the bus acquisition request signal is output by the bus acquisition request signal output unit, the bus cannot be acquired even if the bus acquisition request signal is output. State holding means for transitioning from the first state to the second state when a bus acquisition privilege request signal for requesting output suppression is not output, and returning to the first state when the bus is acquired; A bus acquisition privilege request signal for outputting the bus acquisition privilege request signal to another device when the state holding means is in the second state and the access request destination device is not in a busy state; Signal output means, when the access request destination device is in a busy state,
And suppressing the output of the bus acquisition request signal by the bus acquisition request signal output unit when the state holding unit is in the first state and the bus acquisition privilege request signal is output from another device. Means, each of the devices has a higher priority than its own device when the device itself outputs the bus acquisition request signal and there is no device outputting the bus acquisition privilege request signal. The device that acquires the bus only when the bus acquisition request signal is not output from the first device, the device that outputs the bus acquisition request signal, and the device that outputs the bus acquisition privilege request signal If it exists, the own device outputs the bus acquisition privilege request signal, and the bus is acquired only when the device having higher priority than the own device does not output the bus acquisition privilege request signal. A bus control method characterized by obtaining.