JPS6375827A - Memory device - Google Patents

Abstract

PURPOSE:To increase the write speed or the like by dividing a page buffer memory into plural memory areas and writing data of the next page in the memory area from which data read is terminated. CONSTITUTION:Print data is written in a page buffer memory 9 through a system address bus 1 and a system data bus 2 by the control of a CPU. This memory device is provided with a DMA address bus 3, a DMA data bus 4, an address bus group 5, a data bus group 6, and three-state bi-directional address and data buffer gate groups 7 and 8. The memory 9 consists of plural divided buffer memory areas 1-(n) connected to plural address busses 1-(n) and data busses 1-(n) respectively. Since data of the next page is written in the memory area from which data read is terminated, the capacity of the page buffer memory 9 is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention is a method for reading data blocks from a memory such as a page buffer memory used in a page printer, etc.
The present invention relates to a memory device that reads the same data block or the next data block after the reading is completed, or writes the next data block to the memory while the current data block is being read.

[Prior Art J] This type of memory device is generally connected to two buses, a read bus and a write bus, because the sources for accessing the memory are different for reading and writing. For example, in a device such as a page printer with a slow printing speed, after reading part of the data (for example, 1 byte),
While printing processing such as parallel-to-serial conversion of the data is being performed, the bus used is switched from the read bus to the write bus, and new data is written in the storage area that has already been read. On the other hand, devices with high printing speeds cannot write at the read interval, so
Another same page buffer memory is provided, and one memory writes to the other memory while reading, and when the reading and writing are completed, the reading and writing are exchanged by switching the bus to perform the same processing. .

[Problems to be solved by the invention] However, in such conventional devices, bus switching is constantly required, especially in low-speed devices, and in high-speed devices, the capacity of the page buffer memory is larger than the actual capacity of one page. The drawback of needing twice as much was eliminated.

Therefore, the present invention eliminates the above-mentioned drawbacks and also provides:
By being able to read data from one page buffer memory and write data to that memory at the same time, the memory capacity becomes sufficient for one page, and in addition, a part of the bus, which conventionally had two sets for reading and writing, can be shared. An object of the present invention is to provide a memory device that can be configured as a set of buses by using the following methods.

[Means for Solving Problems 1] In order to achieve the above object, the present invention divides one memory area into a plurality of block areas, provides a gate or selector to connect each block area to a bus, and connects each block area to a bus. Alternatively, reading and writing can be performed simultaneously by writing the next information into the block area from which reading has been completed via a selector.

[Function] In the present invention, the page buffer memory is divided into several memory areas, and the data of the next page is written to the memory area where data reading is completed.
With the page buffer memory for one page, it is possible to achieve the same high read and write speed as a conventional double buffer, and the capacity of the page buffer memory can be cut in half.

Furthermore, according to the present invention, higher speeds can be achieved by simplifying the circuit and printed pattern by sharing a bus and by reducing the number of passing gates on the bus.

[Embodiments] `Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the present invention. Here, 1 is a system address bus, 2 is a system data bus, and these buses do not show print data (:PU (
It is used for writing to the page buffer memory 9 under the control of the central processing unit (Central Processing Unit).

3 is a DMA address bus, 4 is a DMA data bus, and these buses transfer data on the page buffer unmemory 9 to a print data processing section (not shown) via DMA (direct
memory access). 5 is an address bus group (A bus 1 to A bus n), 6 is a data bus group (D bus 1 to D bus n), and both bus groups are divided into n system buses 1 and 2 and a DMA bus. 3.4. Reference numeral 7 denotes a three-state bidirectional address buffer gate group (A gate 0 to A gate n) for switching between writing and reading of the address bus group 5. 8
is a three-state data buffer gate group (D gates 0 to D gates n) that similarly performs writing and reading switching of the data bus group 6.

The page buffer memory 9 is a page buffer memory divided by being connected to a plurality of A buses 1 to n and D buses 1 to n, respectively, and is composed of a plurality of buffer memory areas 1 to n. This buffer memory area 1~
n equals one page. Here, any one of the buffer gates 0 to n indicated by 7 and 8 is always in a high impedance state, and the remaining buffer gates transmit signals. As a result, bus groups 5 and 6 on the system buses 1 and 2 from the high-impedance buffer gate position become system buses, and DMA bus 3
．． The bus group on the fourth side becomes a DMA bus. As a result, the buffer memory areas 1 to n indicated by 9 can be divided at arbitrary positions for writing and reading.

2 to 4 show an example of the operating state of the embodiment of the present invention shown in FIG.

In FIG. 2, it is assumed that data for one page has already been written in the page buffer memory 9. It is assumed that this data is written in order from the start address of buffer memory area 1 indicated by 9 to buffer memory area n. This state will be described as an initial state.

First, gate 0 shown in 7.8 is in a high impedance state, and the remaining gates are in an on state (address gate 7 is
MA address transmission direction), and reading starts from the first data.

After reading out buffer memory area 1, the gate is set to high impedance as shown in Figure 3, and gate 0 is set to high impedance.
Turn on. As a result, the boundary between system buses 1 and 2 and DMA buses 3 and 4 moves to gate 1, data is read from buffer memory area 2, and data of the next page is transferred to buffer memory area 1 from which data has already been read. Writing can be done from buses 1 and 2. In this way, after reading from one buffer memory area is completed, data of the next page can be sequentially written to the buffer memory area from which reading has been completed by shifting the buffer gate that becomes high impedance by one.

After that, as shown in FIG.
When reading is completed, gate n is placed in a high impedance state, and the remaining gates are placed in a conductive state. As a result, all buses connected to the buffer memory 9 become system buses 1 and 2, and all buffer memory areas become writable. In this state, when all data has been written, the high impedance gate becomes gate O again, and the written data can be read as shown in FIG.

Data is read and written by repeating the above operations. In addition, when printing data of the same pattern on many sheets, data for the next page is written while the last page is being read.

In addition, switching the gate that becomes pi impedance or
This can be done automatically by hardware (not shown) immediately after reading from one buffer memory area is finished, but it may also be done by software using an l10 (human output) command.

As described above, according to this embodiment, the same high printing speed as the conventional double buffer can be achieved with the page buffer memory for one page, and the circuit and print pattern can be simplified by using a common bus. It will be done.

In this embodiment described above, the bus is divided into several parts by gates, and each divided bus is connected to the system bus 1.2 and the DMA bus.
Although buses 3 and 4 are shared, the system bus and DMA bus can be switched for each buffer memory area by a plurality of selectors to perform the same operation as in the above embodiment. FIG. 5 shows the structure of another embodiment of the present invention.

In FIG. 5, IO is a system address bus, 11 is a system data bus, 12 is a DMA address bus, and 13 is a DMA data bus. Further, 14 is an address bus selector (A selector), and 15 is a data bus selector (D
16 is a page buffer memory. The page buffer memory 16 includes a plurality of buffer memory areas 1
~ has n.

Initially all selectors 14.15 are on the DMA bus 12.1
3 is selected, print data is read from buffer 1 memory area 1, and print data is read from buffer 1 memory area 1.
Similarly to the final step, after the reading of each buffer memory area 1 to n is completed, the selector is switched to the system bus 10.11 side. This allows the buffer memory area 1 to n
Data can be written to.

Further, by sequentially switching the buffer memory area from which reading has been completed to the system bus 10.11 side using the selector 14.15, reading and writing of data can be performed simultaneously.

After reading all data, switch the last selector n to the system bus 10.11 side to make all buffer memory areas 1 to n indicated by 16 writable, and after writing the next page data, switch all selectors to the system bus 10.11 side. D
Switch to the MA bus side, start reading from buffer memory area 1, and repeat the same operation as described above. In the embodiment shown in FIG. 5, the order in which the buffer memory areas are read can be freely selected. Furthermore, in this embodiment, the number of passing gates on the bus is reduced, so higher speeds can be achieved.

[Effects of the Invention] As explained above, according to the present invention, the page buffer memory is divided into several memory areas, and the data of the next page is written to the memory area from which reading of data has been completed. With a page buffer memory for one page, high read and write speeds similar to those of conventional double buffers can be achieved, and the capacity of the page buffer memory can be reduced by half.

``Furthermore, according to the present invention, higher speeds can be achieved by simplifying the circuit and printed pattern by making the path common, and by reducing the number of passing gates on the path.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing the configuration of a memory device according to an embodiment of the present invention. FIGS. 2 to 4 are state diagrams showing the state of the embodiment of the present invention in operation in FIG. 1. FIG. It is a block diagram which shows the structure of another Example. 1.10--system address bus, 2.11...
System data bus, 3.12... DMA address bus, 4.113... DMA data bus, 5... Shared address bus group, 6... Shared data bus group, 7... Three-state Bidirectional address buffer gate group, 8... Three-state data buffer gate group, 9.
16... Page buffer memory consisting of page buffer memory areas 1 to n divided into n pieces, 14... Address selector, 15... Data selector.

Claims (1)

[Claims] Divide one memory area into a plurality of block areas, provide a gate or selector to connect each of the block areas to a bus, and write the next information into the block area that has been read through the gate or selector. A memory device characterized in that reading and writing can be performed simultaneously.