JPS6372183A - Manufacture of circuit board - Google Patents
Manufacture of circuit boardInfo
- Publication number
- JPS6372183A JPS6372183A JP21667986A JP21667986A JPS6372183A JP S6372183 A JPS6372183 A JP S6372183A JP 21667986 A JP21667986 A JP 21667986A JP 21667986 A JP21667986 A JP 21667986A JP S6372183 A JPS6372183 A JP S6372183A
- Authority
- JP
- Japan
- Prior art keywords
- copper foil
- circuit board
- connection terminal
- etching
- base material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 36
- 239000011889 copper foil Substances 0.000 claims description 34
- 238000005530 etching Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 17
- 230000000873 masking effect Effects 0.000 claims description 16
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 14
- 229910052799 carbon Inorganic materials 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 11
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、回路基板のＩｉｌ造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a circuit board.
（従来の技術）
従来、絶縁性基板面に貼った銅箔に、レジストとなる導
電性カーボンペーストを回路パターン形状に被着し、エ
ツチングして所定の回路パターンを得る回路パターンの
エツチング加工が行なわれている。このエツチング加工
はエツチング後にレジストを除去することなく、そのま
まで回路基板として使用できること、及びレジストは接
点部の酸化防止や回路パターンの腐蝕防止コートとなる
ことより好ましいものである。(Prior art) Conventionally, conductive carbon paste, which serves as a resist, is applied in the shape of a circuit pattern to copper foil attached to the surface of an insulating substrate, and etched to obtain a predetermined circuit pattern. It is. This etching process is preferable because the resist can be used as it is as a circuit board without removing the resist after etching, and the resist serves as a coating to prevent oxidation of the contact portions and prevent corrosion of the circuit pattern.
（発明が解決しようとする問題点）
しかしながら、上記した従来の回路パターンのエツチン
グ加工は形成された回路パターンが導電性カーボンペー
ストよりなるレジストに被われていることより、回路パ
ターンの接続端子部はハンダ付けができず、コネクタを
用いて接続せねばならない問題点があった。そして接ｒ
ｔ端子部に銅箔を残す回路基板のエツチング加工は難し
いものであった。(Problems to be Solved by the Invention) However, in the conventional etching process of the circuit pattern described above, since the formed circuit pattern is covered with a resist made of conductive carbon paste, the connection terminal portion of the circuit pattern is There was a problem in that soldering was not possible and connections had to be made using connectors. and tangent r
Etching of a circuit board that leaves copper foil on the t-terminal portion was difficult.
そこで、この発明は、レジストを施しエツチング加工し
て回路基板を得るに際し、回路パターンの接続端子部を
ハンダ付けし得るようになした回路基板の製造方法を提
供することにある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a circuit board in which connection terminal portions of a circuit pattern can be soldered when a circuit board is obtained by applying resist and etching.
また、この発明は接続端子部が設定位置に正確に形成さ
れるようにした、エツチング加工による回路基板の製造
方法を提供することにある。Another object of the present invention is to provide a method of manufacturing a circuit board by etching, in which connection terminal portions are formed accurately at set positions.
（問題点を解決するための手段）
上記問題点を解決するために、この発明の手段は、
絶縁基材の少な（とも−面に銅箔を接着する第１工程と
、
前記銅箔上に、導電性カーボンペーストを、複数の接続
端子部を含む所定回路パターン形状に被着せしめるとと
もに、接ｖｃ端子部の近傍に位置決めマークを被着せし
めうる第２工程と、前記位置決めマークを基準としてマ
スキングテープにより前記各接続端子部の一部を被覆す
る第３工程と、
前記マスキングテープにより被覆された部分以外の部分
に対し、前記導電性カーボンペーストをレジストとして
エツチングを施し、前記絶縁基材上に前記所定回路パタ
ーンを形成する第４工程と、前記マスキングテープを除
去し、前記各接続端子部の一部に連続する銅箔部を露出
せしめる第５工程と、
よりなる回路基板の製造方法とされる。(Means for Solving the Problems) In order to solve the above problems, the means of the present invention includes: a first step of bonding a copper foil to a small surface of an insulating base material; a second step of applying conductive carbon paste to a predetermined circuit pattern shape including a plurality of connection terminal portions, and also applying a positioning mark near the contact VC terminal portion; and masking using the positioning mark as a reference. a third step of covering a part of each of the connection terminals with tape; etching the parts other than the parts covered with the masking tape using the conductive carbon paste as a resist; and etching the parts on the insulating base material. A method for manufacturing a circuit board, comprising: a fourth step of forming the predetermined circuit pattern; and a fifth step of removing the masking tape to expose a copper foil portion continuous to a part of each connection terminal portion. Ru.
（作 用）
第１工程にて銅箔が接着される。第２工程において銅箔
上に導電性カーボンペーストが被着される。導電性カー
ボンペーストは接続端子部を含む回路パターン部分と、
位置決めマーク部分に同時に塗られてレジストとされる
。第３工程において位置決めマーク位置にマスキングテ
ープが貼られて接続端子部が被覆される。第４工程にて
露出している銅箔はエツチング除去される。第５工程に
て銅箔の露出した接続端子部が形成される。(Function) Copper foil is bonded in the first step. In the second step, a conductive carbon paste is deposited on the copper foil. The conductive carbon paste is applied to the circuit pattern part including the connection terminal part,
It is applied to the positioning mark portion at the same time to form a resist. In the third step, masking tape is applied to the positioning mark position to cover the connection terminal portion. In the fourth step, the exposed copper foil is removed by etching. In the fifth step, connection terminal portions with exposed copper foil are formed.
（実施例） 以下、本発明の一実施例を図面に基づいて説明する。(Example) Hereinafter, one embodiment of the present invention will be described based on the drawings.
まず、第１工程として、例えばフェノール樹脂よりなる
絶縁性基材１の両面に接着剤を介して銅箔２が貼着され
る（第１図参照。なお、各図面は接＠層を省略して描い
である）。次いで前記銅箔２上には導電性カーボンペー
スト３Ａを被着する第２工程の処理がされる。この第２
工程において導電性カーボンペースト３Ａは複数の接続
端子部４を含む所定の回路パターン５形状になるように
被着するとともに両銅箔２面部位の端部側には適宜形状
の位置決めマーク６を被着する（第２図参照）。なお本
例では両銅箔２面に導電性カーボンペースト３Ａを所定
形状となるように印刷により被着した。しかる優、位置
決めマーク６を基準として、マスキングテープ７により
前記各接続端子部４を被覆する第３工程の処理をする（
第３図参照）。マスキングテープ７は後述する銅箔２の
エツチング処理に際して侵されない、耐蝕性の大きい材
質のものが使用され、マスキングテープ７は接着剤ある
いは適宜手段にて銅箔２面に密着するように被覆される
。第３工程の処理をした絶縁性基材１は、１ａ酸溶液等
の銅箔２を溶解するエツチング液中に浸され、絶Ｉ３１
性基材１面に露出する銅箔２をエツチングする第４工程
の処理をする。すなわち、第４工程においてはマスキン
グテープ７により被覆された銅箔部２Ａ及び導電性カー
ボンペースト３Ａにてレジスト被覆される銅箔部２Ｂ以
外の銅箔部２Ｃがエツチング除去され、絶縁基材１上に
前記所定回路パターン５（第４図参照）及び接続端子部
４に連続する銅箔部２Ａが形成される。なお、エツチン
グ処理後の絶縁＋ｉ基材１は水洗し乾燥される。First, as a first step, copper foil 2 is attached to both sides of an insulating base material 1 made of, for example, phenol resin via an adhesive (see Figure 1. Note that the contact layer is omitted in each drawing). ). Next, a second process is performed in which a conductive carbon paste 3A is applied onto the copper foil 2. This second
In the process, the conductive carbon paste 3A is deposited in a predetermined circuit pattern 5 shape including a plurality of connection terminal portions 4, and positioning marks 6 of an appropriate shape are coated on the end sides of both copper foils. (See Figure 2). In this example, conductive carbon paste 3A was applied to two surfaces of both copper foils by printing so as to have a predetermined shape. However, using the positioning mark 6 as a reference, perform the third step of covering each connection terminal portion 4 with masking tape 7 (
(See Figure 3). The masking tape 7 is made of a highly corrosion-resistant material that will not be corroded during the etching process of the copper foil 2, which will be described later, and the masking tape 7 is coated with adhesive or other suitable means so as to adhere tightly to the surface of the copper foil 2. . The insulating base material 1 treated in the third step is immersed in an etching solution that dissolves the copper foil 2, such as a 1a acid solution, and
A fourth step of etching the copper foil 2 exposed on the surface of the transparent substrate is performed. That is, in the fourth step, the copper foil portion 2C other than the copper foil portion 2A covered with the masking tape 7 and the copper foil portion 2B coated with the conductive carbon paste 3A with resist is etched away, and the copper foil portion 2C is removed by etching. A copper foil portion 2A continuous to the predetermined circuit pattern 5 (see FIG. 4) and the connecting terminal portion 4 is formed. Note that the insulation+i base material 1 after the etching treatment is washed with water and dried.
次いで、第５工程として、マスキングテープ７を除去し
、各接続端子部４が連続する銅箔部２Ａを露出せしめて
、回路基板８Ａを得る（第５図参照）。Next, in a fifth step, the masking tape 7 is removed to expose the copper foil section 2A where each connection terminal section 4 is continuous, thereby obtaining a circuit board 8A (see FIG. 5).
しかる後、この回路基板８Ａは打抜き型により抜き加工
されて、銅箔部２Ａが各接続端子４に１対１に対応する
ように形成され、回路基板製品８（第６図参照）とされ
る。Thereafter, this circuit board 8A is punched out using a punching die, and the copper foil portions 2A are formed in one-to-one correspondence with each connection terminal 4, resulting in a circuit board product 8 (see FIG. 6). .
この回路基板製品８は回路パターン５の各接続端子部４
がそれぞれ分離された銅箔部２Ａ〜２Ａに連続するよう
に形成されていることから回路基板製品８の実装の際に
電子部品等を銅箔部２Ａ〜２Ａにハンダ付けすることが
できる。This circuit board product 8 includes each connection terminal portion 4 of the circuit pattern 5.
Since these are formed so as to be continuous with the separated copper foil parts 2A to 2A, electronic components and the like can be soldered to the copper foil parts 2A to 2A when the circuit board product 8 is mounted.
（発明の効果）
本発明は前記した問題解決手段となしたため、前記作用
により所期の問題点が解決される。すなわち本発明によ
れば、第１工程により絶縁基材に銅箔が貼着され、第２
工程においてこの銅箔上には複数の接続端子部を含む所
定回路パターン形状と、接続端子部の近傍に位置決めマ
ークとなる導電性カーボンペーストが被着されてレジス
トが形成され、第３工程により位置決めマークに基づき
マスキングテープが被覆され、次いで第４工程のエツチ
ングにより露出している銅箔部分が除去され、マスキン
グテープを除去して各接続端子部に連続する銅箔が露出
した第５工程の回路基板を得ることができる。(Effects of the Invention) Since the present invention is a means for solving the above-mentioned problem, the desired problem can be solved by the above-mentioned action. That is, according to the present invention, the copper foil is attached to the insulating base material in the first step, and the copper foil is attached to the insulating base material in the first step.
In the process, a resist is formed by depositing a predetermined circuit pattern shape including a plurality of connection terminals on the copper foil and a conductive carbon paste that serves as a positioning mark near the connection terminals, and in the third process, positioning is performed. The masking tape is covered based on the mark, and then the exposed copper foil portion is removed by etching in the fourth step, and the circuit in the fifth step where the masking tape is removed and the continuous copper foil is exposed at each connection terminal part. A substrate can be obtained.
本発明において得られる回路基板は、回路パターン部分
がレジストにて被着されていて接点部の酸化防止や回路
パターンの腐蝕防止コートとなり都合が良いものであり
、かつ各接続端子部はそれに連続する銅箔が露出してい
て直接にハンダ付は可能である。また、本発明において
は第２工程の導電性ペースト被着の際に位置決めマーク
を付すようにしたため、マスキングテープはこの位置決
めマークを基準にして被覆でき、マスキングテープの位
置決めし易く、かつ形成される接続端子部の位置を正確
に形成し得る利点がある。The circuit board obtained in the present invention has the circuit pattern portion coated with a resist, which is convenient for preventing oxidation of the contact portions and preventing corrosion of the circuit pattern, and each connection terminal portion is continuous with the resist. The copper foil is exposed and can be soldered directly. In addition, in the present invention, since positioning marks are attached during the second step of applying the conductive paste, the masking tape can be coated based on the positioning marks, and the masking tape can be easily positioned and formed. There is an advantage that the position of the connection terminal portion can be formed accurately.
図面は本発明の実施工程例を示し、第１図は第１工程処
理後の絶縁性基材の斜視図、第２図は第２工程処理後の
絶縁性基材の斜視図、第３図は第３工程処理後の絶縁性
基材の斜視図、第４図は第４工程処理後の絶縁性基月の
斜視図、第５図は第５工程処理後の絶縁性基材の斜視図
、第６図は回路基板の製品を示す斜視図である。
１・・・絶縁性基材
２・・・銅 箔
２Ａ、２Ｂ、２Ｃ・・・銅 箔 部
３・・・レジスト
４・・・接続端子部
５・・・回路パターン
６・・・位置決めマーク
７・・・マスキングテープ
８Ａ・・・回路基板
出願人 ブラザー工業株式会社
代理人 弁理士 岡田英彦（外３名）第３図
第４図The drawings show examples of implementation steps of the present invention; FIG. 1 is a perspective view of the insulating base material after the first step treatment, FIG. 2 is a perspective view of the insulating base material after the second step treatment, and FIG. 3 is a perspective view of the insulating base material after the second step treatment. is a perspective view of the insulating base material after the third step treatment, FIG. 4 is a perspective view of the insulating base material after the fourth step treatment, and FIG. 5 is a perspective view of the insulating base material after the fifth step treatment. , FIG. 6 is a perspective view showing a circuit board product. 1... Insulating base material 2... Copper foil 2A, 2B, 2C... Copper foil section 3... Resist 4... Connection terminal section 5... Circuit pattern 6... Positioning mark 7 ...Masking tape 8A...Circuit board applicant Brother Industries, Ltd. agent Patent attorney Hidehiko Okada (3 others) Figure 3 Figure 4
Claims (1)
と、 前記銅箔上に、導電性カーボンペーストを、複数の接続
端子部を含む所定回路パターン形状に被着せしめるとと
もに、接続端子部の近傍に位置決めマークを被着せしめ
る第２工程と、 前記位置決めマークを基準としてマスキングテープによ
り前記各接続端子部の一部を被覆する第３工程と、 前記マスキングテープにより被覆された部分以外の部分
に対し、前記導電性カーボンペーストをレジストとして
エッチングを施し、前記絶縁基材上に前記所定回路パタ
ーンを形成する第４工程と、前記マスキングテープを除
去し、前記各接続端子部の一部に連続する銅箔部を露出
せしめる第５工程と、 よりなることを特徴とする回路基板の製造方法。[Claims] A first step of adhering a copper foil to at least one surface of an insulating base material, and applying conductive carbon paste on the copper foil in a predetermined circuit pattern shape including a plurality of connection terminal portions. a second step of applying a positioning mark near the connection terminal portion; a third step of covering a portion of each connection terminal portion with masking tape using the positioning mark as a reference; A fourth step of etching the conductive carbon paste as a resist to form the predetermined circuit pattern on the insulating base material, and removing the masking tape and etching the conductive carbon paste as a resist. A method for manufacturing a circuit board, comprising: a fifth step of exposing a continuous copper foil portion in a part of the circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21667986A JPS6372183A (en) | 1986-09-12 | 1986-09-12 | Manufacture of circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21667986A JPS6372183A (en) | 1986-09-12 | 1986-09-12 | Manufacture of circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6372183A true JPS6372183A (en) | 1988-04-01 |
Family
ID=16692223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21667986A Pending JPS6372183A (en) | 1986-09-12 | 1986-09-12 | Manufacture of circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6372183A (en) |
-
1986
- 1986-09-12 JP JP21667986A patent/JPS6372183A/en active Pending
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