JP2511476B2 - Gold plating method for printed wiring boards - Google Patents
Gold plating method for printed wiring boardsInfo
- Publication number
- JP2511476B2 JP2511476B2 JP26004787A JP26004787A JP2511476B2 JP 2511476 B2 JP2511476 B2 JP 2511476B2 JP 26004787 A JP26004787 A JP 26004787A JP 26004787 A JP26004787 A JP 26004787A JP 2511476 B2 JP2511476 B2 JP 2511476B2
- Authority
- JP
- Japan
- Prior art keywords
- gold plating
- printed wiring
- wiring board
- gold
- circuit pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
本発明はプリント配線板の所定箇所に正確に金めっき
を施すことができる金めっき法に関する。The present invention relates to a gold plating method capable of accurately performing gold plating on a predetermined part of a printed wiring board.
プリント配線板の製造において金めっき層はいくつか
の重要な役割を果たす。まず、金属系エッチングレジス
トとして汎用エッチング液の総てに耐え、防錆力も高
く、又、電気伝導度も高く、従って錆の発生を特に嫌う
箇所や電気抵抗の低い接触面に適用できるので、ニッケ
ルを下地めっきすることによりプリント配線板の端子め
っきとして最適である。 この金めっきは、第５図に示すようにプリント配線板
１に回路パターン２よりも小さな金めっき用露出部３を
形成するようにして金めっきレジスト４を被覆し、次い
で金めっき液に浸漬することによりなされているが、金
めっきレジスト４と回路パターン２と密着性が悪く、金
めっき液により金めっき用露出部３近傍の金めっきレジ
スト４部分が剥離（剥離部分4a）してしまい、設計通り
の正確な金めっきを施すことができないという問題があ
った。The gold plating layer plays several important roles in the manufacture of printed wiring boards. First of all, as a metal-based etching resist, it can withstand all general-purpose etching liquids, has high rust-preventing power, and has high electric conductivity, so that it can be applied to places where rust is particularly disliked and contact surfaces with low electric resistance. It is most suitable for terminal plating of printed wiring board by plating under. In this gold plating, as shown in FIG. 5, a gold plating resist 4 is coated on the printed wiring board 1 so as to form an exposed portion 3 for gold plating that is smaller than the circuit pattern 2, and then immersed in a gold plating solution. However, the adhesion between the gold plating resist 4 and the circuit pattern 2 is poor, and the gold plating resist 4 part near the exposed part 3 for gold plating is peeled off by the gold plating solution (peeling part 4a). There was a problem that the exact gold plating could not be applied.
【発明の目的】 本発明は上記事情に鑑みて為されたものであり、その
目的とするところは、プリント配線板に正確な金めっき
を施すことにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to perform accurate gold plating on a printed wiring board.
本発明のプリント配線板の金めっき法は、プリント配
線板１に回路パターン２よりも小さかな金めっき用露出
部３を形成するようにして金めっきレジスト４を被覆
し、次いで金めっきを施すプリント配線板の金めっき法
において、金めっきレジスト４を被覆する前に金めっき
用露出部３近傍の回路パターン２を部分的に除去してプ
リント配線板１の基板６を露出させて成ることを特徴と
するものであり、この構成により上記目的が達成された
ものである。即ち、金めっきレジスト４とプリント配線
板１の露出した基板５が接着して回路パターン２との密
着性が向上し、金めっきを施す際に金めっき液により金
めっき用露出部３近傍の金めっきレジスト４部分が剥離
することがなく、設計通りに金めっきを施すことができ
るものである。 以下、本発明の添付の図面を参照して説明する。 本発明におけるプリント配線板１は、銅張積層板から
常法により回路パターン２が形成されたものである。第
１図に示す実施例にあっては、スルーホール６近傍に金
めっきを施そうとするものである。まず、回路パターン
２に形成する金めっき用露出部３に沿うように二条の切
欠部2aを形成して基板５を露出させておく。次に、円形
の金めっき用露出部３を形成するようにしてプリント配
線板１に金めっきレジスト４を被覆する。金めっきレジ
スト４は切欠部2aを介して基板５と接着し、金めっきレ
ジスト４と回路パターン２との密着性が良好なものとな
る。次に、金めっき液に浸漬して金めっき用露出部３に
金めっきを施す。金めっき液はプリント配線板や金めっ
きレジストの劣化を抑制するために酸性浴ないしは中性
浴が好ましい。この後は、金めっきレジストを除去して
所定の箇所に金めっきが施されたプリント配線板１を得
る。 尚、第２図に示すように、スルーホール以外の箇所に
も金めっき用露出部３を形成するようにしてもよく、
又、第３図に示すように略Ｙ字状に切り欠いて切欠部2a
を形成してもく、更に、第４図に示すように複数個の切
欠部2aを形成するようにしてもよい。In the method for gold-plating a printed wiring board according to the present invention, the printed wiring board 1 is coated with a gold-plating resist 4 so as to form an exposed portion 3 for gold plating that is smaller than the circuit pattern 2, and then a gold-plating print is performed. In the method of gold-plating a wiring board, the circuit pattern 2 in the vicinity of the gold-plating exposed portion 3 is partially removed before the gold-plating resist 4 is covered to expose the substrate 6 of the printed wiring board 1. The above object is achieved by this configuration. That is, the gold plating resist 4 and the exposed substrate 5 of the printed wiring board 1 adhere to each other to improve the adhesiveness with the circuit pattern 2, and the gold in the vicinity of the exposed portion 3 for gold plating is enhanced by the gold plating solution when gold plating is performed. The plating resist 4 portion is not peeled off, and gold plating can be applied as designed. Hereinafter, the present invention will be described with reference to the accompanying drawings. The printed wiring board 1 in the present invention has a circuit pattern 2 formed from a copper clad laminate by a conventional method. In the embodiment shown in FIG. 1, gold plating is to be applied near the through hole 6. First, the two notches 2a are formed along the exposed portion 3 for gold plating formed on the circuit pattern 2 to expose the substrate 5 in advance. Next, the printed wiring board 1 is coated with the gold plating resist 4 so as to form the circular gold plating exposed portion 3. The gold plating resist 4 adheres to the substrate 5 through the notch 2a, and the adhesion between the gold plating resist 4 and the circuit pattern 2 becomes good. Next, the exposed portion 3 for gold plating is subjected to gold plating by immersing it in a gold plating solution. The gold plating solution is preferably an acidic bath or a neutral bath in order to suppress the deterioration of the printed wiring board and the gold plating resist. After that, the gold plating resist is removed to obtain the printed wiring board 1 in which gold plating is applied to predetermined portions. Incidentally, as shown in FIG. 2, the gold plating exposed portion 3 may be formed in a portion other than the through hole,
Further, as shown in FIG. 3, a notch 2a is formed by notching in a substantially Y shape.
Alternatively, a plurality of notches 2a may be formed as shown in FIG.
本発明は、プリント配線板に回路パターンよりも小さ
な金めっき用露出部を形成するようにして金めっきレジ
ストを被覆し、次いで金めっきを施すプリント配線板の
金めっき法において、金めっきレジストを被覆する前に
金めっき用露出部近傍の回路パターンを部分的に除去し
てプリント配線板の基板を露出させているので、金めっ
きレジストを被覆したときに、金めっきレジストとプリ
ント配線板の露出した基板が接着して回路パターンとの
密着性が向上し、金めっきを施す際に金めっき液により
金めっき用露出部近傍の金めっきレジスト部分が剥離す
ることがなく、設計通りに金めっきを施すことができる
ものである。The present invention covers a gold plating resist on a printed wiring board so as to form an exposed portion for gold plating that is smaller than a circuit pattern, and then coats the gold plating resist in a gold plating method of a printed wiring board for performing gold plating. The circuit pattern in the vicinity of the exposed portion for gold plating is partially removed before exposing the printed wiring board substrate, so when the gold plating resist is covered, the gold plating resist and the printed wiring board are exposed. The adhesion of the board improves the adhesion to the circuit pattern, and the gold plating solution does not peel off the gold plating resist portion near the exposed portion for gold plating when gold plating is performed, and gold plating is performed as designed. Is something that can be done.
第１図は本発明の一実施例を示す概略図、第２図、第３
図及び第４図は本発明の他の実施例を示す概略図、第５
図は従来例を示す概略図であって、 １はプリント配線板、２は回路パターン、３は金めっき
用露出部、４は金めっきレジスト、５は基板である。FIG. 1 is a schematic view showing an embodiment of the present invention, FIG. 2 and FIG.
4 and 5 are schematic views showing another embodiment of the present invention, and FIG.
1 is a schematic view showing a conventional example, 1 is a printed wiring board, 2 is a circuit pattern, 3 is an exposed portion for gold plating, 4 is a gold plating resist, and 5 is a substrate.
Claims (1)
な金めっき用露出部を形成するようにして金めっきレジ
ストを被覆し、次いで金めっきを施すプリント配線板の
金めっき法において、金めっきレジストを被覆する前に
金めっき用露出部近傍の回路パターンを部分的に除去し
てプリント配線板の基板を露出させて成ることを特徴と
するプリント配線板の金めっき法。1. A method for coating a printed wiring board with a gold plating resist so as to form an exposed portion for gold plating that is smaller than a circuit pattern, and then performing gold plating on the printed wiring board. A method for gold plating of a printed wiring board, characterized in that the circuit pattern in the vicinity of the exposed portion for gold plating is partially removed before coating to expose the substrate of the printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26004787A JP2511476B2 (en) | 1987-10-15 | 1987-10-15 | Gold plating method for printed wiring boards |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26004787A JP2511476B2 (en) | 1987-10-15 | 1987-10-15 | Gold plating method for printed wiring boards |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01101693A JPH01101693A (en) | 1989-04-19 |
| JP2511476B2 true JP2511476B2 (en) | 1996-06-26 |
Family
ID=17342563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26004787A Expired - Lifetime JP2511476B2 (en) | 1987-10-15 | 1987-10-15 | Gold plating method for printed wiring boards |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2511476B2 (en) |
-
1987
- 1987-10-15 JP JP26004787A patent/JP2511476B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01101693A (en) | 1989-04-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0226620B1 (en) | Method of manufacturing printed circuit boards | |
| US4925525A (en) | Process for producing a printed circuit board | |
| JP2511476B2 (en) | Gold plating method for printed wiring boards | |
| JPH035078B2 (en) | ||
| JPH01290289A (en) | Method of forming conductor pattern | |
| JP2741238B2 (en) | Flexible printed wiring board and method of manufacturing the same | |
| JPH0573359B2 (en) | ||
| JPH1079568A (en) | Manufacturing method of printed circuit board | |
| JP2000091722A (en) | Printed wiring board and its manufacture | |
| JPS6336598A (en) | Manufacture of wiring board | |
| JP3439779B2 (en) | Manufacturing method of printed wiring board and printed wiring board | |
| CA2224188A1 (en) | Parts-packaging substrate and method for manufacturing same as well as method for manufacturing a module | |
| JPS6210039B2 (en) | ||
| JPS6031116B2 (en) | Electric wiring circuit board and its manufacturing method | |
| JPS61193315A (en) | Manufacture of smoothing switch substrate | |
| JPS63283098A (en) | Formation of pattern | |
| JPS5892291A (en) | Method of producing printed circuit board | |
| JPH0680893B2 (en) | Method for manufacturing metal-based double-sided flexible circuit board | |
| JPH03194992A (en) | Manufacture of printed board | |
| JPS62242393A (en) | Flexible printed wiring board and manufacture of the same | |
| JPH0719949B2 (en) | Flexible wiring board manufacturing method | |
| JPH0327588A (en) | Manufacture of circuit board | |
| JPH10335788A (en) | Formation of wiring pattern | |
| JPH0748583B2 (en) | Method for manufacturing electrical inspection jig board for high-density printed wiring board | |
| JPS6372183A (en) | Manufacture of circuit board |