JPS6372166A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make the title device multifunctional and highly speedy, and to prevent the generation of big stepped parts and to improve a yield by a method wherein a superlattice is formed on the side of a mesa which is composed of more than one semiconductor layers including a heterojunction on a substrate. CONSTITUTION:For the manufacutre of a semiconductor device, an i-type GaAs active layer 2 and an n<+> type AlGaAs electron supply layer 3 are first formed on a semi-insulating GaAs substrate 1, and, by etching the n<+> type AlGaAs electron supply layer 3 and the i-type GaAs active layer 2, a mesa is then formed. Then, after an AlGaAs film 4 has been formed, the AlGaAs film 4 is etched by anisotropic etching so that only a coated part on the side of the mesa remains unetched. Then, the formation of films by means of a molecular beam epitaxy method and the anisotropical etching process by means of a reactive ion etching method are repeated so that a GaAs film 5, an AlGaAs film 6 and an n-type GaAs electrode contact layer 7 can be formed. Then, from an SL on both sides of the mesa and the electrode contact layer 7, e.g., the part on the right side is removed. Then, a source electrode 8, a drain electrode 9 and a gate electrode 10 to be located on the surface of the electron supply layer 2 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention provides a method for manufacturing a semiconductor device, in which a superlattice is formed on the side surface of a mesa consisting of a plurality of semiconductor layers including a heterojunction on a substrate. This makes it possible to obtain a functionally high-speed semiconductor device, and also eliminates the difficulty of the process in manufacturing a semiconductor device having a superlattice.

[Industrial application field]

The present invention relates to a method suitable for manufacturing a semiconductor device having a new function by combining a vertically formed heterojunction and a horizontally formed heterojunction.

[Conventional technology]

In recent years, there has been active development of semiconductor devices that utilize heterojunctions or super lattices (SL) consisting of multiple heterojunctions, such as high electron mobility transistors (SL).
capacity transistor: HEMT),
hot electron transistor
electrontransistor (HET), resonant tunneling hot electron transistor (r
esonant-tunneling hotel
ctron transistor (RHET) and the like are known.

[Problem that the invention seeks to solve]

Most of the heterojunction semiconductor devices mentioned above are extremely fast compared to, for example, normal field effect semiconductor devices, but this is their only advantage and unless they are specially configured, they do not have any other special functions. There are many things I don't have.

In addition, since the various conductor layers are stacked vertically, heterojunctions are also created vertically, which causes various problems in the manufacturing process, such as isolation between elements. It is necessary to perform deep etching to form electrode lead-out parts, and the separation between elements is approximately 1 [μm].
It is not uncommon for some degree of etching to be required, and moreover, complex step-like mesa etching must be performed to lead out the electrodes, resulting in a very poor manufacturing yield for this type of semiconductor device. There is.

By configuring a semiconductor device by forming heterojunctions in the vertical and horizontal directions, the present invention provides functions not found in conventional semiconductor devices, prevents the occurrence of large steps, and speeds up the manufacturing process. To increase yield by being easy and to manufacture at low cost.

[Means for solving problems]

In the method for manufacturing a semiconductor device according to the present invention, a plurality of semiconductor layers (for example, an i-type GaAs active N
2 and n-type Al1GaAs electron supply layer) in the vertical direction, patterning the semiconductor layer to form a mesa, and forming a barrier semiconductor layer (for example, AJGaAs film 4) on the sides of the mesa. and 6) and a step of forming a superlattice made of a semiconductor layer (for example, the GaAs film 5) that will become a well.

[Effect]

By adopting the above method, it is possible to obtain a semiconductor device having a heterojunction in the vertical direction and a superlattice in the horizontal direction, which is not only high-speed but also a heterojunction semiconductor having, for example, differential negative characteristics. The device can be manufactured easily, and furthermore, in the heterojunction semiconductor device, it is possible to perform isolation between elements without creating a large step on the surface. Since difficulties in the manufacturing process are eliminated, the yield is improved, and as a result, semiconductor devices with high speed and special functions can be provided at low cost.

〔Example〕

1 to 8 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures. Note that here, a resonant tunneling diode (resonant-tu
The target is the case where a semiconductor device is manufactured by combining an internal ring diode (RTD) and a HEMT.

See Figure 1 (11 molecular beam epitaxial growth (molecular beam epitaxial growth)
By applying the beam epitaxy (MBE) method, i-type GaAs is deposited on the semi-insulating GaAs substrate 1.
s active layer 2, n+ type Aj! GaAs electron supply N3 is formed.

An example of the main data of each semiconductor layer in this case is as follows.

■ Thickness of active layer 2: 300 (people) ■ X value of electron supply layer 3: 0.3 Thickness: 200 (people) Impurity concentration: I x 10I8 (cm-') See Figure 2 (2) Normal Resist process in photolithography technology and reactive ion etching using CF4 as etching gas
By applying the on etching (RIE) method, the n + type AlGaAs electron supply layer 3 and the i type GaA
s The active layer 2 is etched to form a mesa.

The size of this mesa is, for example, 1 [μm] in plan view.
]×10 [μm] is selected.

By applying the +31MBE method (see Figure 3), the thickness can be reduced to
Aj of [person]! A GaAs film 4 is formed.

See Figure 4. (4) By applying the RIE method using CF4 as the etching gas, the AlGaAs film 4 is anisotropically etched, leaving only the part adhered to the side surface of the mesa and removing the rest. do.

See Figure 5. (5) As mentioned above, film formation by MBE method and R
By repeating the anisotropic etching using the IE method, a GaAs film 5 having a thickness of, for example, 50 mm, and a GaAs film 5 having a thickness of, for example, 50 mm are formed.
An n-type GaAs electrode contact N7 is formed using an AfGaAs film 6 having a thickness of, for example, 1,000 mm.
The impurity concentration of the electrode contact layer 7 is I x 10I8 (
ell-') may be used.

AJGaAs film 4 formed as described above, GaAs
Membrane 5, Aj! It goes without saying that the GaAs film 6 constitutes the SL, and these may be formed into multiple layers if necessary.

Refer to FIG. 6 (6) By applying a normal photolithography technique, of the SL and electrode contact layers 7 on both sides of the mesa, for example, the one on the right side is removed.

See FIG. 7. (7) A source electrode 8 and a drain electrode 9 are formed by applying a resist process and a lift-off method of normal photolithography technology. In addition, the material constituting the source electrode 8 and drain electrode 9 is A
G e / A u are used, and their thickness is 200 [
) / 800 (persons) is good.

See FIG. 8. (8) Gate electrode 10 is formed on the surface of electron supply layer 3 by applying a resist process and lift-off method of normal photolithography technology. Note that Aj2 is used as the material of the gate electrode 10, and its thickness is 3.
Good as 000 (person).

In addition, the symbol 11 seen in FIG. 8 indicates the two-dimensional electron gas layer generated on the active layer 2 side near the hetero interface composed of the active layer 2 and the electron supply layer 3, and the symbol 12 indicates the RTD part. are instructed respectively. In addition, in the RTD portion 12, an AlGaAs film 4, a GaAs film 5, and an Aj2GaAs
The 6° portion of the membrane acts as SL.

Drain-source voltage v0 vs. drain current (■) in the semiconductor device thus fabricated.

The relationship is as seen in Figure 9.

In Figure 9, the horizontal axis represents the drain-source voltage VO.
S is plotted on the vertical axis, and drain current ID is plotted on the vertical axis, and characteristic lines are shown for cases where the gate voltage (1) is O(V) and a positive value, respectively.

As is clear from the characteristic line shown, the semiconductor device of the present invention has negative differential characteristics. For example, even if the gate voltage (19) is different, the drain current 1111 depends on the drain-source voltage VDS. Sometimes they are the same and sometimes they are different.

Since such characteristics are obtained, it is possible to perform logical operation or oscillation operation.

〔Effect of the invention〕

In the method for manufacturing a semiconductor device according to the present invention, a superlattice is formed on the side surface of a mesa made of a plurality of semiconductor layers including a heterojunction on a substrate.

By adopting the above structure, it is possible to obtain a semiconductor device having a heterojunction in the vertical direction and a superlattice in the horizontal direction, which is not only high-speed but also a heterojunction semiconductor having, for example, differential negative characteristics. The device can be manufactured easily, and in the heterojunction semiconductor device, it is possible to perform isolation between elements without creating a large step on the surface, eliminating difficulties in the manufacturing process. As a result, the yield is improved, and as a result, this type of semiconductor device can be provided at low cost.

[Brief explanation of the drawing]

1 to 8 are cut-away side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and FIG. Each diagram represents a diagram for explaining the characteristics of a semiconductor device manufactured in this manner. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an i-type GaAs substrate, and 2 is an i-type GaAs substrate.
AS active layer, 3 is n-type AlGaAs electron supply layer, 4 is A
1GaAs film, 5 is GaAs film, 6 is A I Ga
7 is an n+ type electrode contact layer, 8 is a source electrode, 9 is a drain electrode, 10 is a gate electrode, 11 is a two-dimensional electron gas layer, and 12 is an RTD portion. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Akira Aitani Representative Patent Attorney Hiroshi Watanabe - Figure 1 Figure 2 Figure 3 Figure 6 Figure 7

Claims (1)

[Claims] A step of vertically stacking and growing a plurality of semiconductor layers including at least one heterojunction on a substrate, a step of patterning the semiconductor layer to form a mesa, and a side surface of the mesa. 1. A method of manufacturing a semiconductor device, comprising: forming a superlattice made up of a semiconductor layer serving as a barrier and a semiconductor layer serving as a well.