JPS6370999A - Variable stage shift register - Google Patents

Abstract

PURPOSE:To set the optional number of shift stages through a simple constitu tion by controlling the write and the read of input data by using a random access memory, and controlling an address corresponding to a selective signal. CONSTITUTION:A variable stage shift register is provided with a shift register 1, which outputs a read timing signal, a write timing signal and a count clock signal, with an n-ary system counter 2, which presets the selective signal by a carry signal and outputs an address after counting up the count clock signal from the shift register 1, and with a RAM 3, which is accessed by the address from the n-ary system counter 2 and writes input data by the timing signal from the shift register 1 and reads the written data by the read timing signal. If the selective signal to be preset in the n-ary system counter 2 is made to be (a), the data written in the n-the address of the RAM 3 comes to be the shift register of n-a stage. Thus, the desired number of the shift stages can be set by the selective signal.

Description

[Detailed Description of the Invention] [Summary] A shift register with an arbitrary number of shift stages is configured by performing write control and read control of input data using a random access memory, and controlling addresses corresponding to a selection signal. .

[Industrial application field]

The present invention relates to a variable stage shift register in which the number of shift stages can be arbitrarily set.

A shift register sequentially shifts input data according to a clock signal, and has various uses. For example, since a delay time corresponding to the number of shift stages can be obtained, it is used as a data delay circuit. It is also used in a synchronization circuit that synchronizes frame data by controlling the delay time. It is desired that such a shift register has a simple configuration and can provide an arbitrary number of shift stages.

[Conventional technology]

Conventional shift registers for making the number of shift stages variable are:
For example, as shown in FIG. 4, a plurality of shift register units 11, 12.1 having the same or different numbers of shift stages
3.14 are connected in cascade, input data is shifted sequentially according to a clock signal (not shown), and the output of each shift register section 11, 12, 13, 14 can be selected by a selector 15, and a selection signal The shift register sections 11, 12, 13 are selected by the selector 15,
．． 14 outputs are selected and used as output data.

Assuming that the number of shift stages of each shift register section 11.12, 13.14 is n, when the selector 15 selects the output of the shift register section 12 according to the selection signal, the shift register becomes a 2n stage shift register. Similarly, when the selector 15 selects the output of the shift register section 13 according to the selection signal, the shift register becomes a 3n-stage shift register.

Further, by preparing shift register sections each having a different number of shift stages and inputting input data to the shift register section selected by a selector, a shift register having a desired number of shift stages can be constructed.

[Problem that the invention seeks to solve]

Since the number of stages in the shift register section is limited, it is difficult to obtain an arbitrary number of shift stages, and increasing the number of shift stages has the drawback of increasing the circuit scale.

It is also conceivable to control the number of shift stages by control of a microprocessor, but this has the drawback of increasing the cost required for software development.

An object of the present invention is to enable the number of shift stages to be arbitrarily set using a simple configuration.

[Means for solving problems]

The variable stage shift register of the present invention will be described with reference to FIG. 1. The shift register 1 outputs a read timing signal, a write timing signal, and a count clock signal.
and an n-ary counter 2 which presets a selection signal using a carry signal, counts up a count clock signal from a shift register 1, and outputs an address signal;
A random access memory 3 is accessed by the address from the n-ary counter 2, input data is written in by the write timing signal from the shift register 1, and the written data is read by the read timing signal, and is shifted by the selection signal. This is to set the number of stages.

[Effect]

If the selection signal to be preset to the n-ary counter 2 is a, it becomes a (na)-ary counter, and the data written to the n address of the random access memory 3 is written after (na) count clock signals. Since it is read out, it becomes a (na) stage shift register. Therefore, the desired number of shift stages can be set by the selection signal.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is a shift register, 2 is an n-ary counter, 3 is a random access memory (RAM), and 4 is an inverter. The input category is applied to the data input terminal Din of the random access memory 3, and output data is sent out from the data output terminal pout.

In addition, the input clock signal synchronized with the input data is shifted by the shift register 1 and sent to the random access memory 3.
Write control terminal W, ! :A write timing signal and a read timing signal are respectively applied to the read control terminal R, and a count clock signal CL is applied to the n-ary counter 2.

The n-ary counter 2 presets a selection signal when the carry signal from the carry terminal CR is applied to the load terminal via the inverter 4, and the count contents are applied to the address terminal A O of the random access memory 173.
- added to Am.

FIG. 2 is a timing explanatory diagram of an embodiment of the present invention, and (
a) is the input clock signal, (b) is the count clock signal CL applied to the n-ary counter 2, IC) is the address signal of the count output of the n-ary counter 2, (d+ is the read timing signal, (e) is the write These are timing signals.The count clock signal, read timing signal, and write timing signal are each formed by sequentially shifting a manual clock signal.

FIG. 3 is an explanatory diagram of the operation of the embodiment of the present invention, where n=16
The selection signal to be preset to the n-ary counter 2 is set to “1”.
000'', therefore, the address signal applied to the random access memory 3 is at times tQ and tl.
, t2. "1000" to "11" in order according to ...
11''. When the random access memory 3 is accessed by the address signal, data is first read out by the read timing signal, and input data is written to that address by the write timing signal.

Therefore, data written first from address "1000" at time tQ is read out in accordance with the read timing signal, input data is written in accordance with the next write timing signal, and this data is read out at time t8. At time t1 “
The data written first from the address 1001'' is read out according to the read timing signal, the input data is written according to the next write timing signal, and this data is read out at time t9. “1” at t7
The data written to addresses from 010'' to 1111'' is read out from time tlO to t15. In other words, an 8-stage shift register is configured.

Therefore, a shift register having a desired number of shift stages can be configured by the selection signal preset to the n-ary counter 2.

〔Effect of the invention〕

As explained above, in the present invention, the number of shift stages can be set by the selection signal sent to the n-ary counter 2, and the read timing signal and write timing signal of the random access memory 3 are inputted. This can be easily obtained by shifting the clock signal. Therefore, there is an advantage that a shift register having an arbitrary number of shift stages from 1 to n stages can be constructed with a simple structure.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a timing explanatory diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of operation of an embodiment of the present invention, and Fig. 4 is a block diagram of a conventional example. It is. 1 is a shift register, 2 is an n-ary counter, 3 is a random access memory (RAM), and 4 is an inverter.

Claims (1)

[Scope of Claims] A shift register (1) that shifts an input clock signal and sequentially outputs a read timing signal, a write timing signal, and a count clock signal; and a shift register (1) that presets a selection signal by a carry signal; ) an n-ary counter (2) that counts a count clock signal from the n-ary counter (2) and outputs an address signal; and a write timing signal that is accessed by the address signal from the n-ary counter (2) and outputs the write timing signal from the shift register (1). a random access memory (3) into which input data is written, read out by the read timing signal, and outputted shift output data of the number of shift stages determined by the selection signal. register.