JPS6370161U - - Google Patents
Info
- Publication number
- JPS6370161U JPS6370161U JP16421086U JP16421086U JPS6370161U JP S6370161 U JPS6370161 U JP S6370161U JP 16421086 U JP16421086 U JP 16421086U JP 16421086 U JP16421086 U JP 16421086U JP S6370161 U JPS6370161 U JP S6370161U
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- lead frame
- island
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第1図は本考案の実施例を示す樹脂封止半導体
装置の下面図、第2図は本考案の樹脂封止半導体
装置の概略斜視図、第3図は従来の樹脂半導体装
置のリードフレームの平面図、第4図は従来の樹
脂封止半導体装置の斜視図、第5図はアイランド
各辺下部樹脂モールド部に発生する応力分布図、
第6図は従来装置の応力分布の説明図、第7図は
本考案の装置の応力分布の説明図、第8図は実施
例に基づく効果の説明図、第9図は更なる問題点
を説明する半導体装置の部分断面図、第10図は
本考案の他の実施例を示す樹脂封止半導体装置の
部分断面図である。 21,31,41,51,61……アイランド
、22,52,62……リード端子、23,53
,63……半導体素子、24,54,64……A
uワイヤ、25,55,65……パツケージ、2
7……ベント孔、28,42,58,68……突
起、28a……R部、28b,68b……傾斜部
、30,32……樹脂モールド部。
装置の下面図、第2図は本考案の樹脂封止半導体
装置の概略斜視図、第3図は従来の樹脂半導体装
置のリードフレームの平面図、第4図は従来の樹
脂封止半導体装置の斜視図、第5図はアイランド
各辺下部樹脂モールド部に発生する応力分布図、
第6図は従来装置の応力分布の説明図、第7図は
本考案の装置の応力分布の説明図、第8図は実施
例に基づく効果の説明図、第9図は更なる問題点
を説明する半導体装置の部分断面図、第10図は
本考案の他の実施例を示す樹脂封止半導体装置の
部分断面図である。 21,31,41,51,61……アイランド
、22,52,62……リード端子、23,53
,63……半導体素子、24,54,64……A
uワイヤ、25,55,65……パツケージ、2
7……ベント孔、28,42,58,68……突
起、28a……R部、28b,68b……傾斜部
、30,32……樹脂モールド部。
補正 昭62.10.2
図面の簡単な説明を次のように補正する。
明細書の第14頁第11行目に記載の「25,
55,65……パツケージ」を「25,30,3
2,55,65……モールド部」と補正する。 明細書の第14頁第13行目に記載の「30,
32,……樹脂モールド部」を削除する。
55,65……パツケージ」を「25,30,3
2,55,65……モールド部」と補正する。 明細書の第14頁第13行目に記載の「30,
32,……樹脂モールド部」を削除する。
Claims (1)
- 【実用新案登録請求の範囲】 (1) 半導体素子が固着され、その周囲が樹脂モ
ールド封止されるリードフレームのアイランドの
各辺の中央部にアイランド裏面と同一平面上に延
びる突起を設けると共に、該突起の基部にRを形
成するようにしたことを特徴とする樹脂封止半導
体装置のリードフレーム。 (2) 前記突起はその先端方向に向かつて厚さが
薄くなるように形成してなる実用新案登録請求の
範囲第1項記載の樹脂封止半導体装置のリードフ
レーム。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986164210U JPH0447966Y2 (ja) | 1986-10-28 | 1986-10-28 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986164210U JPH0447966Y2 (ja) | 1986-10-28 | 1986-10-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6370161U true JPS6370161U (ja) | 1988-05-11 |
JPH0447966Y2 JPH0447966Y2 (ja) | 1992-11-12 |
Family
ID=31093119
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986164210U Expired JPH0447966Y2 (ja) | 1986-10-28 | 1986-10-28 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0447966Y2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009060093A (ja) * | 2007-08-06 | 2009-03-19 | Seiko Instruments Inc | 半導体装置 |
JPWO2019116457A1 (ja) * | 2017-12-13 | 2020-05-28 | 三菱電機株式会社 | 半導体装置及び電力変換装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4967552U (ja) * | 1972-09-28 | 1974-06-12 | ||
JPS53124068A (en) * | 1976-12-27 | 1978-10-30 | Hitachi Ltd | Lead frame |
-
1986
- 1986-10-28 JP JP1986164210U patent/JPH0447966Y2/ja not_active Expired
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4967552U (ja) * | 1972-09-28 | 1974-06-12 | ||
JPS53124068A (en) * | 1976-12-27 | 1978-10-30 | Hitachi Ltd | Lead frame |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009060093A (ja) * | 2007-08-06 | 2009-03-19 | Seiko Instruments Inc | 半導体装置 |
JPWO2019116457A1 (ja) * | 2017-12-13 | 2020-05-28 | 三菱電機株式会社 | 半導体装置及び電力変換装置 |
Also Published As
Publication number | Publication date |
---|---|
JPH0447966Y2 (ja) | 1992-11-12 |