JPS6369479A - Phase control circuit - Google Patents

Abstract

PURPOSE:To extremely shorten a time required for phase lead-in, by diminishing a phase error on the phase lead-in. CONSTITUTION:By a timing circuit 12, reference clock, phase signal, and state signal showing whether phase is controlled or not are received, and the output of set signal and latch signal is generated. By a counter circuit 13, according to the timing of the phase signal, its counting value is set to be a value on the lead-in of the phase control. By a latch circuit 14, the counting value of the counter circuit 13 is latched. Accordingly, the counting value of the latch circuit 14 is almost in the state of the lead-in of the phase control, also when the value is shifted to the state of the phase control, and the lead-in time of the phase control is extremely shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a phase control circuit for a capstan motor or the like used in a video tape recorder or a digital audio tape recorder.

BACKGROUND OF THE INVENTION In recent years, in controlling the capstan motor of a video tape recorder, the circuit speed is multiplied by FG, converted to frequency information, and the period of this FC signal is counted by a counter operating with a reference clock. , a method is adopted in which the result is DA-converted and fed back to the motor drive circuit.

A conventional phase control circuit will be described below with reference to the drawings.

FIG. 4 is a block diagram of an example of a conventional phase control circuit, in which 41 is a latch pulse generation circuit, 42 is a latch circuit, and 4 is a block diagram of an example of a conventional phase control circuit.
3 is a phase error gate circuit, 44 is a phase comparison counter, 4
5 is a gate circuit, 46 is a preset circuit, 47 is a preset pulse generation circuit, 48 is a decoder, and 49 is a preset value generation circuit.

The operation of the phase control circuit configured as above will be explained below.

First, a latch pulse generation circuit 41 generates a latch pulse from a comparison signal and a clock pulse, and a latch circuit 42 latches the output of the phase error gate circuit 43 using the latch pulse to detect a digital phase error. On the other hand, a preset pulse generating circuit 47 generates a preset pulse of one clock width from the reference signal and a clock pulse, and a preset circuit 46 generates a phase comparison counter 44 using the output of the preset value generating circuit 49 as a counting start value using the preset pulse. Preset to . Further, the internal reference signal is generated by detecting the count value of the phase comparison counter 44 with a gate circuit 45.

[For example, National Technical Review) cNati
-onal Technicai Report) 2nd
Volume 8, No. 3, pages 191 and 192].

Problems to be Solved by the Invention However, in the above configuration, the phase comparison counter continues counting by clock pulses, and the phase of the comparison signal is synchronized with the phase comparison counter, so the response time may vary due to the control characteristics of the phase system, etc. Therefore, if the phase error is large during phase pull-in, there is a problem that the pull-in time becomes longer.

In view of the above-mentioned problems, the present invention provides a phase control circuit with a short phase pull-in time by reducing the phase error during phase pull-in.

Means for Solving the Problems In order to solve the above problems, the phase control circuit of the present invention has the following steps:
a reference signal generation circuit that outputs a reference clock; a timing circuit that receives the reference clock, a phase signal that performs phase control, and a status signal that indicates whether or not to perform phase control, and outputs a set signal and a latch signal; , a counter circuit that performs counting in response to a reference clock and sets a predetermined constant value in response to a set signal, and a latch that latches the count value of the counter circuit in response to a latch signal and outputs it as a phase error output. It is equipped with a circuit.

Effect of the Invention With the above-described configuration, the present invention makes it possible to set the count value of the counter circuit to the value when the phase control is pulled in according to the timing of the phase signal that performs the phase control without performing the phase control.

Therefore, the count value of the latch circuit that latches the count value of the counter circuit is almost in the phase control state even when the state is shifted to the phase control state, and the phase control pull-in time is extremely shortened.

Embodiment Hereinafter, a phase control circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a phase control circuit in an embodiment of the present invention. In FIG. 1, 11 is a reference signal generation circuit, 12 is a timing circuit, 13 is a counter circuit, and 14 is a timing circuit.
indicates a latch circuit. FIG. 2 is a circuit diagram showing a specific example of FIG. 1. 21 is a reference signal generation circuit, 22 is a timing circuit, 23 is a 4-bit counter circuit, 24 is a 4-bit latch circuit that latches at a rising edge, 2
5.26 is a D flip-flop, 27 is a NAND gate, and 28 is an OR gate. Further, FIG. 3 is an operation diagram for explaining the operation of FIG. 2. The operation shown in FIG. 2, which is an example of the unit shown in FIG. 1, will be explained using the operation diagram shown in FIG. 3.

In the specific example shown in FIG. 2, since the counter circuit 23 is a 4-bit counter, the frequency at which the phase signal is synchronized is minus the frequency of the reference clock output from the reference signal generation circuit 21. Further, FIG. 3 shows the operation of FIG. 2 when the value of the counter 23 is α when the phase control is retracted.

In FIG. 2, the reference signal generation circuit 21 is shown in FIG. 3(a).
As shown in the figure, a reference clock having a frequency 16 times that of the phase signal to which phase control is applied is output. The timing circuit 22 includes D flip-flops 25 and 26 and a NAND gate 27.
A latch signal is created from the rising edge of the phase signal.

The phase signal is shown in FIG. 3(b), and the latch signal is shown in (C1).The D flip-flops 25 and 26 are latch signals because they operate at the falling edge of the reference clock that is the output of the reference signal generation circuit 21. The output signal of the NANT) gate 27 changes state in synchronization with the falling edge of the reference clock. First, let's look at the state where no phase control is performed, that is, when the logical value of the state signal is low 1/bell (hereinafter abbreviated as below).
It is shown in section g of the figure. The state signal is shown in FIG. 3 (dl). The output of the OR gate 28, which is the set signal, is equal to the output of the NAND gate 27 because the state signal is L.

The set signal is shown in FIG. 3 (i).While the logic of the set signal is being maintained, the counter circuit 23 sets the set value α at the timing of the rising edge of the reference clock. Then, when the latch signal rises, the latch circuit 24 latches the value α set in the counter circuit 23. Therefore, when the status signal is ◯, the set value α is set in the counter circuit 23 at the rising timing of the phase signal, and at the same time, the set value α is also latched in the latch circuit 24. The counted value of the counter circuit 23 is shown in FIG. 3ff).

Next, consider a state in which phase control is performed, that is, when the state signal is at a high level (hereinafter abbreviated as 11). In FIG. 3, this corresponds to section h. Since the state signal is H, the output of the OR gate 28 is always I], and the counter circuit 23 starts counting from the last value α set in the 6th section. Therefore, (a is set) of the counter circuit 23 that is latched first in the h interval.

This value does not deviate significantly from the initial value α, and the counter circuit 23 can count the phase signal very quickly. Thereafter, while the state signal is 14, the count value of the counter circuit 23 is roughened to the latch circuit 24 at the rising edge timing of the phase signal, and is output as a phase error.

Although the counter circuit 23 has 4 bits in the embodiment shown in FIG. 2, it can have any number of bits since the count number can be determined from the frequency of the phase control and the frequency of the reference clock.

Effects of the Invention As described above, the present invention includes a reference signal generation circuit that outputs a reference clock, a reference clock, a phase signal that performs phase control, and a status signal that indicates whether or not to perform phase control. , a timing circuit that outputs a set signal and a latch signal, a counter circuit that performs counting in response to a reference clock, and a predetermined constant value is set to 1 in response to a set signal, and a counter circuit that outputs a set signal and a latch signal; By providing a latch circuit that receives a latch signal, latches a numerical value, and outputs it as a phase error output, the time required for phase control pull-in can be extremely shortened.

Therefore, for example, if the phase control circuit of the present invention is used in a capstan motor of a digital audio recorder, not only will the phase pull-in time of the capstan motor be shortened and the mode transition time, but also the phase control circuit with respect to the reference clock will be reduced. When transitioning from a playback state in which no recording is performed to a recording state in which phase control is performed, the rotational phase of the capstan motor becomes extremely small, making stable post-recording possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a phase control circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a specific example of the configuration of FIG. 1, and FIG. 3 is an operation explaining the operation of FIG. 2. 4 are block diagrams showing an example of a conventional phase control circuit. 11...Reference signal generation circuit, 12...
Timing circuit, 13...Counter circuit, 14
...Latch circuit.

Claims (1)

[Claims] A reference signal generation circuit that outputs a reference clock, a phase signal that performs phase control on the output of the reference signal generation circuit, and a status signal that indicates whether the phase error output of the phase control circuit is used for control or not is latched. a timing circuit that outputs a set signal when the signal and status signal do not indicate a phase control state; and a timing circuit that receives the output of the reference signal generation circuit, performs counting, and receives the set signal output of the timing circuit and generates a predetermined constant value. A counter circuit whose value can be set,
a latch circuit that receives a latch signal output from the timing circuit, latches the counted value of the counter circuit, and outputs it as a phase error output, and the state signal indicates that the phase error output of the phase control circuit is not used for control. When showing
A phase control circuit characterized in that by forcibly setting a count value of a counter circuit, a phase error output is used to shorten phase control pull-in time when entering a phase control state.