JPS5967884A - Control system for rotor - Google Patents

Abstract

PURPOSE:To shorten the phase synchronization drawing time by locking a discriminating wave at the center of operation by a signal from phase detecting means out of range of discriminating frequency, thereby specifying the phase error after entering into the range of discriminating the frequency to L or H level. CONSTITUTION:When a digital frequency discriminator (D.F.D.) 5 is out of discriminating range, a digital phase comparator (D.P.C.) 13 is forcibly locked by a PS signal (d). A phase error (g) after the D.F.D. 5 enters into the discriminating from out of discriminating range is compared with an inner reference signal (e), it is always specified to L level when the frequency of the signal (d) is low, and to H level in reverse case thereto. Accordingly, the frequency of the signal (d) is raised when the error (g) is L level to advance the phase by applying an acceleration command to a speed control loop, and when the error is H level, a deceleration command is applied to delay the phase.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a control system for rotating a rotating body in phase synchronization with a predetermined reference signal.

Structure of a conventional example and its problems FIG. 1 shows a conventional example of a digital control system for a rotating body.

In FIG. 1, 1 is a rotating body and its drive motor, and 2 is a frequency detection means (hereinafter FG) for detecting the number of rotations of the motor 1.
3 is a speed control means that controls the rotation speed of the motor 1 by frequency-discriminating the output of FG2 (FG multiplier signal A), and these components form a speed control loop.Speed control Means 3 is a digital frequency discrimination circuit (digital frequency discrimination circuit) which digitally discriminates frequencies by inputting the FG signal doubler and the first clock pulse from the input terminal 4.
D, F, D) 5 and D, F, D 5 to DA
A mixing circuit (mix) that mixes the converted and output speed error (x) and the phase error (x) that is DA converted and output from the digital phase comparator circuit (D, P, C) 13 (described later) 6 and a drive circuit (M, D) 7 that drives the motor 1 using the output of Mix 6 as input.

Reference numeral 8 indicates a phase detection means (hereinafter referred to as PCi) for detecting the rotational phase of the motor 1, and 9 indicates a phase error obtained by comparing the phase of the output of PGa (PG multiplied signal) and the internal reference signal (O). The phase control means 9 controls the rotational phase of the motor 1 by controlling the speed control means 3, and these components form an inverse phase control loop. 1) and the second clock pulse from the input terminal 10, a latch pulse (7) and a predetermined inhibit voltage are applied at the time of latching.
) Launch pulse generation circuit (L, P, G) 1
1, a preset pulse generation circuit (P, P, G) that generates a preset pulse from an internal reference signal (second clock pulse) 12, L, P
, Digital phase comparison that digitally compares the phase of the output of G11 (7 shaku (ke) and the output of P, P, G (cono) and the internal reference signal (, f) and PG multiplied signal 1). Circuit (D, P, C) 13 and D, P, C
The reference signal generation circuit (R, S, G) 14 generates an internal reference signal (force) by detecting a predetermined count value of .

If 15 burrs, F, D 6 are within the range of frequency discrimination, then I
Frequency discrimination detection circuit (F, D, D or 16 detects phase error (K-Off operation center Reference voltage generation circuit g (R, V, G) that generates the reference voltage ('/) corresponding to the voltage, 17F, D
, the output of D16 (?NOBI L When II, outputs the reference voltage (≧2, and the output (t) d: When it is "H'", outputs the phase error (S, w).

FIG. 2 shows operational waveforms of the main parts of FIG. 1. Symbols in FIG. 2 correspond to those in FIG. 1, and the operating waveforms of O, D, P, and C13 are DA-converted and displayed.

Digitally create a trapezoidal wave with the internal reference signal (pl according to (6)), P, and C13, and latch it with the latch pulse (η) created from the PG signal generator to obtain the phase error (ki). D, F, D ts is outside the discrimination range, F, D, D 15t7) output (-tJka” L
” ), the reference voltage (shi) of R, V, and G16 is S,
The output of Wl (-51, l), E', and D6 are within the range of discrimination, and F, D, and D are the output of 15 (the man is I
When T H11 is reached, the phase error (the phrase is S, the output of Wl7 (Snow). This causes Ip D, F, D 5
Outside the discrimination range of
V, forced to the reference voltage (shi) of G16, D, F,
The phase synchronization pull-in time of the phase control loop after D5 enters the discrimination range is shortened.

However, in such a conventional configuration, I′iF, D, D 15
There is no guarantee that the phase error (K) at the timing when the output (S) changes from "L" to '1 ('K) is a voltage that speeds up phase synchronization, and L n , + "H'"
, I don't know which one will be at the intermediate level. For this reason, F
, D, D After switching from the reference voltage (R) to the phase error (K) at the output (S) of D15, the phase synchronization pull-in time of the phase control loop becomes long.

OBJECTS OF THE INVENTION It is an object of the present invention to eliminate such conventional drawbacks and shorten the phase synchronization pull-in time of the phase control loop.

Structure of the Invention The present invention includes a frequency detection means for detecting the rotation speed of a rotating body;
speed control means for controlling the rotational speed of the rotary body based on the output obtained by frequency discrimination of the output of the frequency detection means; phase detection means for detecting the rotational phase of the rotary body; and a phase control means for controlling the rotational phase of the rotating body by controlling the speed control means based on the output obtained by comparing the phase with the output of the detection means, and the speed control means has a frequency discrimination range. When the frequency is outside, the phase control means is set to a center value for phase comparison operation by the output of the phase detection means, and when the frequency is within a frequency discrimination range, the cent operation is stopped by the output of the phase detection means. It is something to do.

DESCRIPTION OF EMBODIMENTS FIG. 3 shows one embodiment of the present invention, FIGS. 4 and 5 are operational waveform diagrams for explanation, FIG. 6 shows another embodiment of the present invention, and FIG. 9 to 9 are operational waveform diagrams for explanation. Hereinafter, the differences between the present invention and the conventional one will be explained with reference to the drawings.

Figure 3 shows R, V, G16 and s, from the conventional example in Figure 1.
'By removing w17 and using the outputs 1 and 2 of F, D, and D15 as new inputs for P and G11, L,
Input the preset pulse (:1) newly created in P and G11 to the OR gate 18 to selectively output the preset pulse (SEN) and the preset pulse (:1) of P, P, and G12, and then output the OR output (S2, P , C1a's new preset pulse, and precent pulse (ce), P,
It is configured to be used as a preset value (NP) switching signal for C13. Note that the other configurations are the same as those in FIG. 1, and the numbers and symbols also correspond.

The present invention will be explained in detail with reference to FIG. 4.
A new preset pulse ~ is created using P and G11, but this preset pulse is a pulse that at least precedes the launch pulse (7) in terms of timing, and the outputs of F, D, and D15 are L I+ It is configured to output when +1 HI+ and not output when +1 HI+.

Then, from the preset value NP when presetting with a preset pulse (when presetting with a preset pulse (ko) with a preset pulse), P
By switching and presetting the value NC that is the center of the phase comparison of , C13, D, P, and C13 are forcibly locked by the PG signal, and the phase error outside the discrimination range of F, D5 is prevented. The pheasant is obtained as the output of S, #17 in Figure 1 (equivalent to the scallop).

Next, when D, F, and D5 are within the discrimination range, the preset pulse is not output and the precent operation is possible only with the precent pulse □□□.
This allows for normal phase comparison.

With this configuration of the present invention, the phase error after F and D5 enter the discrimination range from outside the discrimination range can be calculated as shown in the figure when the frequency of the PG signal is lower than the internal reference signal O. Always at °I L 1" level, and vice versa °゛H
``H'' level is possible, so the phase error is n
When the L I+ level is present, an acceleration command is given to the speed control loop to increase the frequency of the PG signal and advance the phase, and the HI
At + level, a deceleration command can be given to delay the phase.

That is, in the present invention, since the phase control loop can have unidirectionality during transition, the phase synchronization pull-in time can be shortened.

FIG. 5 is a waveform diagram showing DA conversion and display for explaining how to use the counters No. 3, P, and C13 in FIG.

Taking as an example a configuration that creates a slope part of a trapezoidal wave C to obtain a phase error (K) from the lower N bits B of an M-bit down counter 8, the count values NH, NL of the slope part and the operation are as follows. The center value NC is determined, and the count values NP and NF are determined from the ratio of the leading phase period and the slow phase period E of the trapezoidal wave C. NP is a preset value, and NF is a feedback count value that becomes an internal reference signal.

In this way, if the trapezoidal wave C is arbitrarily created from the M-bit counter A, the operation center value NC for phase comparison can be an arbitrary binary number, so the preset pulse can be cut as shown in Figure 3. When presetting, set the preset values of P and C13 to N using the preset pulse (Se).
It is necessary to switch from P to NC. Normally this operation is RO
Do it with M.

FIG. 6 shows another configuration example in which the preset value switching shown in FIG. 3 is removed. The differences from the configuration in Figure 3 are P, P, and G12.
From +) set pulse (ri) to set pulse (te),
Create a reset pulse (horn) from L, P, and G11, and take the output (TE) obtained by ORing the reset pulse (9 and (horn) with the OR gate 18, and use it as the reset input for P and C13.
This is the point where the cent pulse (te) is used as the set input for D, P, and C13.

The reset pulse (T9 is the same as how to make the preset pulse (C) in Figure 3, but the reset pulse (R) of p, P, (-212) and the cent pulse (C) are different from each other in terms of timing. It is necessary that the pulse has an overlapping portion and that at least the cent pulse (chi) is a pulse that changes after the reset pulse reno.

7 to 9 show examples of the use of the M-bit counter applicable to FIG. 6.

First, in Fig. 7, the central operating value NC of beams P and C13 is M
The count value of the bit counter is O2, that is, a binary number A L L
The case where the point ``O''' is selected is shown. With such a configuration, the operation center value NC in FIG. 3 is preset to 1 (it does not need to be done by switching the OM, and can be done with a reset operation. In addition, in FIG. 8]), P, and the operation of C13. This shows how to use the center value NC as the Nth bit, only 1 is 1111+, and all other bits are 0'''. In this case, only the Nth bit needs to be used by switching the set/reset inputs. In this case, It is necessary to invert the polarity of the Nth bit of the preset value NP.Furthermore, FIG.
, shows an example of use in which the lower (N-1) bit of the operating center value NC of C13 is set to 0'', and the upper bits from the N-th bit to the M-th bit are set to 1''.In this case, from the N-th bit to the M-th bit The set/reset inputs of the upper bits up to the upper bits may be exchanged, and the preset value NP may be obtained by reversing the polarity of all upper bits from the 1st N bit to the Mth bit.

By using the system as described above, it becomes unnecessary to switch preset values in order to set the operating center value NC.

Note that the present invention can achieve the same effect even when applied in addition to the conventional configuration, and the phase detection means 8 is also used as the frequency detection means 2, and the output of the frequency detection means 2 (FG multiplied signal A) is The same effect can be obtained even if the M-bit counter is used in a step-down manner.Furthermore, the M-bit counter is not limited to the illustrated down counter, and the control method of the rotating body is not limited to the digital method.

Effects of the Invention As described above, the present invention employs a method of locking the trapezoidal wave as the center of operation from the PG multiplied signal outside the range of frequency discrimination.
Since the phase error after entering the range of frequency discrimination can be regulated to the "L" level or the "H" level, it is possible to achieve the effect of further shortening the phase synchronization pull-in time compared to the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional control method for a rotating body, FIG. 2 is an operation waveform diagram of FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the rotating body control method of the present invention. 4 and 5 are operation waveform diagrams of the same embodiment, FIG. 6 is a block diagram showing another embodiment of the present invention, and FIGS. 7, 8, and 9 are diagrams of the implementation of FIG. 6, respectively. FIG. 4 is an example operational waveform diagram. 1...Rotating body, 2...Frequency detection means,
3... Speed control means, 8... Phase detection means, 9... Phase control means. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 Figure 5 Figure 7

Claims (4)

[Claims] (1) a frequency detection means for detecting the number of rotations of a rotating body; and a speed control means for controlling the number of rotations of the rotating body based on an output obtained by frequency-discriminating the output of the frequency detection means;
The rotation of the rotary body is controlled by a phase detection means for detecting the rotational phase of the rotary body, and a reference signal that is generated and the speed control means is controlled based on the output obtained by comparing the phase with the output of the phase detection means. and a phase control means for controlling the phase, and when the speed control means is outside the range of frequency discrimination, the phase control means is set to the operation center value of the phase comparison by the output of the phase detection means, A control method for a rotating body, characterized in that a set operation based on the output of the phase detection means is stopped when the output is within a range. (2) A control system for a rotating body according to claim 1, wherein the phase detection means is configured to step down the output of the frequency detection means. (3) The phase control means is constituted by a binary counter, and when the speed control means is outside the range of frequency discrimination, the binary counter is set to a count value corresponding to the operation center value of the phase comparison by the output of the phase detection means. A control method for a rotating body according to claim 1, characterized in that presetting is performed. (4) a frequency detection means for detecting the number of rotations of the rotating body; and a speed control means for controlling the number of rotations of the rotating body based on the output obtained by frequency-discriminating the output of the frequency detection means;
A phase detecting means for detecting the rotational phase of the rotary body, and a speed control means for generating a reference signal and comparing the phase with the output of the phase detecting means to control the speed control means. and a phase control means for controlling the rotational phase, and when the speed control means is outside the range of frequency discrimination, the phase control means is set to the operating center value of the phase comparison by the output of the phase detection means, and the phase The phase control means outputs a reference voltage substantially equal to the operating center value in place of the output of the control means, and stops the set operation based on the output of the phase detection means when the frequency is within the range of frequency discrimination, and in place of the reference voltage, the phase control means A control method for a rotating body characterized by outputting an output of .