JPS6194579A - Digital type phase controller - Google Patents

Abstract

PURPOSE:To shorten a phase pull-in synchronization at starting or speed converting time by controlling a digital filter in response to the state of the speed comparison of speed comparing means. CONSTITUTION:A frequency generator 2 outputs a signal SFG of the frequency proportional to the rotating speed of a unit 1 to be controlled, and a rotary position detector 6 outputs a signal SPG representing a rotary phase. Speed comparing means 3 discriminates the frequency of the signal SFG and outputs digital speed information DS1. Phase comparing means 7 applies phase error information DP1 between the signal SPG and an external reference signal SRF through a digital filter 8 to the means 3. A digital filter 4 digitally processes the information DS1, and applies it to drive means 5. State detecting means 18 detects the state of the speed comparison of the means 3 to control the states of the filters 4, 8.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital phase control device for controlling the rotational phase of a controlled object.

Configuration of conventional example and its problems Figure 1 shows a conventional example of a digital phase control device.
is a controlled object (a motor or a rotating body driven by a motor), 2 is a frequency generator (hereinafter referred to as FG), 3 is a digital speed comparison means, 4 is a digital filter, 5 is a driving means, and 6 is a rotational position detection 7 is a digital phase comparison means, and 8 is a digital filter.

The number of rotations of the controlled object, that is, the rotation speed, is detected by FG2 as a signal with a frequency proportional to the speed (FG multiplied signal SFG), and a signal representing the rotational phase (PG multiplied signal SPG is detected as P
Detected by Ge. FG multiplication signal FG is speed comparison means 3
is input, and its frequency is digitally discriminated (speed comparison) using a clock pulse CK1 to detect digital speed error information Ds1. The speed error information Ds1 is digitally processed by a digital filter 4, and its digital output Ds2 is guided to a driving means 5 to control the rotational speed of the controlled body 1. On the other hand, PG signal SPG external reference signal S
Clock pulse C
K2 digitally discriminates (phase compares) the phase difference between the two signals and detects digital phase error information DP1.

The phase error information DP1 is digitally processed by a digital filter 8, and its digital output DP2 is guided to the speed comparator 3 to control the rotational phase of the controlled object 1. As described above, a digital phase control device is realized which synchronizes the rotational phase of the controlled object 1 (signal 5PG) with the reference phase (signal "RF").

First, the operation of the speed comparison means 32 and the phase comparison means 7 will be explained with reference to FIGS. 2 and 3.

The speed comparison means 3 has an FG multiplied signal FG and a clock pulse C.
K1 is input, and a latch pulse SL1 that precedes the timing and a preset pulse SP1 that follows are created. Normally, the speed comparison means 3 is composed of an M-bit binary counter, and is configured to detect speed error information Ds1 from the lower N bits thereof, and digitally creates an equivalent trapezoidal wave SZ1 using the preset pulse 'PR. , is latched by latch pulse SL1 to obtain speed error information Ds1. T is the reference period for speed comparison, and TFG is the period of the FG multiplied signal FG. A is in a low speed state when FG > T i, B is in a constant speed state when TFG=T, and C is in a constant speed state when FG < ”
i is a high speed state, state A latches (samples) the minimum value of the trapezoidal wave S21, state B the center value, and state C the maximum value, respectively. In state A, acceleration is performed, and in state C, deceleration is performed. It is controlled to be stable at B.

The external reference signal SRF, the PG signal SPG, and the clock pulse OK2 are input to the phase comparison means 7, and a preset pulse SP2 is created using the external reference signal SRF.
A latch pulse SL2 is created using the double signal PG. Like the speed comparison means 3, the position comparison means 7 is composed of a K-bit binary counter, and the phase error information DP is obtained from the lower L bits.
1, and the preset pulse SP2
Digitally create an equivalent trapezoidal wave S22 by
The phase error information DP is latched by the latch pulse SL2.
I got 1.

The illustrated state is a steady state, and the center position of the slope of the trapezoidal wave S22 created using the external reference signal SRF is set to the PG multiplied signal P.
It is latched with the latch pulse SL2 created in G.

When this state breaks down and the trapezoidal wave S22 is in a fast phase state where the upper base is latched, and in a slow phase state where the lower base is latched, the phase error information DP1 has its maximum value.

Since this is the minimum value, it is possible to bring the controlled body 1 into a steady state (phase synchronized state) by controlling the controlled body 1 to be slow or fast. This can be realized by a configuration in which the digital output DP2 obtained by digitally processing the phase error information DP1 by the digital filter 8 is guided to the speed comparison means 3 and controlled. Methods for controlling the speed comparison means 3 using the digital output "P2" include: (1) adding it to the speed error information Ds1, and (2) modulating the reference period T1. Needless to say,
Since the phase comparison means 7 has a binary counter configuration, it is possible to decode a predetermined count value to generate an internal reference signal and use it in place of the external reference signal SRF, and the PG multiplied signal PG is the FG multiplied signal. A configuration in which FG is frequency-divided and used is also possible.

Next, the configuration and operation of the digital filters 4 and 8 and their influence on the system shown in FIG. 1 will be explained using a specific example shown in FIG.

FIG. 4A shows an up/down counter type digital filter (U/D counter type, F), and FIG. 4B shows a cumulative addition type digital filter (cumulative addition type, F). The basic components of the digital filter are a frequency dividing means 9 and a U/D counter 11 for the U/D counter type, and an adding means 14 and a delay means (storage means) 15 for the cumulative addition type. It will be done. The multiplication means 12.16 and the addition means 13.17 are means for adding proportional characteristics, respectively, thereby obtaining proportional-integral characteristics. U/D counter type, F operates by inputting clock pulse CK3 in frequency dividing means 9 to digital signal D1 (DSll
The frequency is divided into a frequency equal to the absolute value of the difference between the reference digital signal Do (corresponding to DPl) and the reference digital signal Do, and the divided output S1 is
It is used as a clock input for the counter 11. On the other hand, in the size determining means 10. and Dl,
The output S2 is used as the U/D switching input. This allows U
An integral output D2 (corresponding to DS2 and DP2) of Dl with Do as a reference value is obtained from the /D counter 11.

Here, the size determining means 10 is not necessarily necessary, and the
When setting a specific value such as 1o...0 (also 01...1), it is possible to use the most significant bit of input D1 as the U/D switching input. . According to the cumulative addition formula, the operation of F is such that the output value of the addition means 14 is stored in the storage means 16, and the output D5 and the input D1 are added to the addition means 14.
Add with . As a result, an integral output D2 (corresponding to Ds2.DP2) of the input D1 is obtained from the adding means 14.

Normally, the storage operation of the storage means 15 involves the latch pulses SL1. of the speed comparison means 32 and the phase comparison means 7. SL2 is used respectively. Incidentally, the coefficient multiplied by the multiplication means 12.16 is a real number including 1, and the proportional integral output D4 (corresponding to Ds2.DP2) is obtained from the addition means 13.17.

These digital filters are applied to the 4°8 means of FIG. 1 as integral elements or proportional-integral elements as required. However, when the controlled object 1 is activated or speed is changed, the output D2. of the U/D counter 11.degree.
D5 is not necessarily specified, and the phase control device cannot be pulled into phase synchronization smoothly and quickly. this is,
U/D counter 11. This is due to the initial state of the storage means 16.

That is, for example, if it is not possible to output the maximum value (or a nearby value) when decelerating the controlled object 1 and output the minimum value (or a nearby value) when accelerating the controlled object 1, the U/D counter type , F, it is necessary to wait for the up or down count operation, and it takes a lot of time to pull in phase synchronization. There were problems such as the value or maximum value being held, making it impossible to perform phase synchronization pull-in.

OBJECTS OF THE INVENTION The present invention solves the problems of the above-mentioned conventional examples, and aims to provide a digital phase control device that reduces phase synchronization pull-in during startup, speed switching, and the like.

Composition of the Invention The present invention is configured to control the digital filter constituting the digital phase control device according to the speed comparison state of the speed comparison means, thereby shortening the phase synchronization pull-in time at startup or speed switching. It is possible.

DESCRIPTION OF EMBODIMENTS The configuration and operation of the present invention will be explained below using embodiments. Fifth
The figure is an electrical block diagram of a digital phase control device showing an embodiment of the present invention.

In FIG. 5, reference numeral 18 denotes a state detection means for detecting the speed comparison state of the speed comparison means 3;
The difference from the conventional example shown in FIG. 1 is that the state of the digital filters 4 and 8 is controlled by the detection output S3 of the filter 8. The main points of the present invention will be explained below.

Normally, the speed comparison means 3 operates as shown in FIG. 2, and the signal 5NH1SNL shown in FIG. 6 is used to form the trapezoidal wave SZ1.
has been created and used. This is a signal necessary to take out the lower N bit output from the M-bit binary counter forming the speed comparison means 3 only for one cycle before the end of counting. SNH is a signal for setting the "Hn level period A" of the trapezoidal wave SZ1, and SNL is a signal for setting the "L" level period C. These two signals determine the speed comparison period beginning in which speed comparison errors can be detected. Here, period C is a period during which the controlled object 1 should be accelerated, and period B is a period during which it should be decelerated, and both speed pull-in and two-phase pull-in are impossible.Therefore, in this period, , the output S3 of the state detection means 18 causes the digital filter 4 to output an acceleration command, the digital filter 8 to output a phase advance command,
In period A, control is performed to output a deceleration command from the digital filter 4 and a slow phase command from the digital filter 8.

Next, since both speed pull-in and two-phase pull-in are possible at the beginning of the period, the control in periods A and N is canceled, and the digital filters 4 and 8 are immediately set to the steady state of speed pull-in and 1-phase pull-in. , thereafter, the control by the state detection means 18 is released. In this way, the phase synchronization pull-in of the phase control device, which is the object of the present invention, can be carried out smoothly and quickly, and the pull-in time can be shortened.

FIG. 7 shows a specific circuit example of the state detection means 18, which generates a signal S3 for controlling the digital filter 4.8 from the speed comparison means 5NH2SNL. FIG. 8 shows the operation waveforms of FIG. 7, where A shows the operation during acceleration (startup) and B shows the operation during deceleration.

In FIG. 7, 19 is a first shift register, 20 is a second shift register, 1sA, 1sB.

2OA, 20B are D7 lip-flops (DFF), 19
C is a two-man NAND gate (2NAND), 20C, 2
0D is a two-person NOR game) ('2NOR). The signals SNH and SNL are respectively D of the first shift register 19.
D input of FF19A, 19B, latch pulse SL1
latches. The Q output of DFFlsA is the signal 5E (
H), and the Q output of DFF19B is 2NAND
At 19C, perform NAND with the signal NL and output the signal RE(L
). Next, signals SE (c), RE (L)
are DFF2OA of the second shift register 20, -
20B and is latched by latch pulse SL1 or preset pulse SP1. 2NoR20C performs NOR between the Q output of DFF20A and signal 5E (H) and outputs 9 signal RE(E()), and 2NOR20D' performs NOR between the Q output of DFF20B and signal RE (L) and outputs signal 5E. These four types of signals 5E(
E(), RE(I,), RE(c).

5E(L) is the detection output S3 of the state detection means 18,
It is used to control the digital filters 4 and 8 as necessary. Note that the DFFs 19B and 2N of the first shift register 19
AND19C is a start command function provided in the normal speed comparing means 3, and does not necessarily need to be newly provided in the state detecting means 18.

FIG. 9 shows an embodiment of a digital filter controlled by the output S13 of the state detection means 18. In Figure 9,
A is a U/D counter type, and F is a U/D counter type 1.
1, B is a cumulative addition type, and F is a configuration that controls the storage means 15.

FIG. 10 shows the U/D counter 11. of FIG. Storage means 15
This is a specific circuit example for explaining the control method.

In FIG. 10, flip-flops FF1 to FFs correspond to the binary counter of the U/D counter 11 and the latch circuit of the storage means 16, respectively. A can only be used during acceleration, and during the period, FF1 to F can be controlled by the signal RE (L).
All Fs are reset and minimum values, that is, acceleration commands and phase advance commands are output. At the beginning of the period, the reset operation by the signal RE (L) is canceled, and only the MSB FFa is turned on by the signal 5.
Instantaneous setting is performed by E(L) to set the central value, and thereafter the control of FF1 to FFs is released. This reduces the amount of time required to pull in from low speeds. B can be applied during acceleration and deceleration, and all FF1 to FFs have a set human power S and a reset input H. The control when transitioning from period No. to the period opening is the same as in A, and the control when transitioning from period A to the period opening is added using the newly installed 2OR gates 21 and 22. That is, in period A, all FF1 to FFa are set by the signal 5E(E(), and the maximum value, that is, the deceleration command and the slow phase command are output. At the beginning of the period, the signal R is set.
E(H) instantaneously resets the lower bits FF1 to FFT and sets them to the center value, and thereafter the control of FF1 to FFs is released. This makes it possible to shorten the pull-in from low speeds and high speeds.

FIG. 11 shows another embodiment of the digital filter. The difference from the embodiment in FIG. 9 is that output gate means 23 and 24 are added and the configuration is controlled by the output S3 of the state detection means 18, and the state detection means 18 and the U/D counter 11
．． This makes it possible to simplify the storage means 16. Note that the output gate means 23 may be configured to gate-output the output D4 of the addition means 13, and the output gate means 24 may be configured to gate-output the output D6 of the storage means 15 or the output D4 of the addition means 17.

FIG. 12 shows the U/D counter 11. of FIG. Storage means 1
5. This is a specific circuit example for explaining a method of controlling the output gate means 23 and 24. Figure 12A.

B is an example of a circuit corresponding to FIG. 10A and H, respectively.
Reset FT, set FFs to center value,
The output gate means 26 is configured to output the output of the FFs via a 2AND gate 25A, and is controlled by an inverted output from the inverter 26 to make the output D2' the minimum value. Then, when the period starts, this control is canceled. Also, in B, in addition to A, in period A, FF1 to FFs are set to the center value by signal 5E(E()) via 20R gate 27,
The output gate means 26 is configured to output the outputs of the lower pins FF1 to FF7 via 20R gates 26B to 25H, and is controlled by the signal 5E()() to make the output D2' the maximum value.

Then, when the period starts, this control is canceled.

Note that during period C, 20R gates 25B to 25HK are open, and during period A, 2AND gate 25A is open. With the above configuration, the second shift register 20 of the state detection means shown in FIG. 7 can be made unnecessary, and the flip 70 knobs FF1 to FFs can only have one function of setting or resetting. The configuration can be simplified.

The specific example of the digital filter described above can be commonly used for the digital filters 4 and 8 shown in FIG. 5, and smooth and speedy phase synchronization, which is the object of the present invention, can be achieved.

Here, if the method of controlling the reference period Ti f' of (2) is adopted as a method of controlling the speed comparing means 3, the digital filter 8 is replaced with the output gate means 25. The configuration is such that the inverter 26 is removed, and only the center value setting of FF1 to FFs is required.

The above description is one embodiment of the present invention, and it goes without saying that various configurations are possible without departing from the spirit of the present invention.

Since the digital filter is controlled according to the effect state of the invention, the synchronization pull-in of the phase control device can be shortened, and its practical effects are excellent.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional digital phase control device, Figures 2 and 3 are operating waveform diagrams of the conventional example, Figure 4 is a block diagram of a digital filter used in the conventional example, and Figure 5 is a block diagram of a digital phase control device. The figure is a block diagram of a digital phase control device according to an embodiment of the present invention, FIG. 6 is an operation waveform diagram of the embodiment, FIG. 7 is a specific circuit diagram of the state detection means of the embodiment, and FIG. 8 is the same. FIG. 9 is an operational waveform diagram of a specific circuit example, and FIG.
Fig. 0 is a partial specific circuit diagram of the same embodiment, Fig. 11 is a block diagram of a digital filter of another embodiment that can be applied to the embodiment of the present invention, and Fig. 12 is a partial specific circuit diagram of the same embodiment. be. 3... Speed comparison means, 4, 8... Digital filter, 5... Drive means, 7...
...Phase comparison means. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4 (Al /θ (s'', 6 Figure 5 Figure 6 Figure 7 Figure 7 5E(t)□゛RE(H) Figure 9 (A) Figure 10 (, 41 Figure 11 Figure 12 (AI D2'

Claims (3)

[Claims] (1) A phase comparison means that digitally detects phase error information of the controlled object, a digital filter that digitally processes the output of the phase comparison means, and a digital filter that digitally detects the speed error information of the controlled object. and a state detecting means for detecting a speed comparison state of the speed comparing means, the digital filter is controlled by the output of the state detecting means, and the controlled object is controlled by the output of the digital filter. A digital phase control device characterized by controlling a rotational phase. (2) The speed comparison means is controlled by the output of the digital filter, and the rotational phase of the controlled object is controlled by the output of the speed comparison means.
The digital phase control device described in . (3) A second digital filter for digitally processing the output of the speed comparison means, which controls the second digital filter by the output of the state detection means and is controlled by the output of the second digital filter. 3. The digital phase control device according to claim 2, wherein the digital phase control device controls the rotational phase of a body.