JPS636899Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bit-variable sign bit expansion circuit that expands the sign bit area so that signed input data becomes signed data with a desired bit length longer than the input data.

When handling digital data,
When input data is signed data, such as 9-bit long data or 8-bit long data, and is fed to a 12-bit arithmetic unit or control device for processing, the most significant bit of the data is generally is treated as a sign bit, processing becomes easier if the sign bit of input data less than 12 bits is converted to a signed 12-bit length that is easier to handle by the arithmetic unit or control unit.

In particular, when processing the bit length of the data part excluding the sign bit as constant, out of the 12 bit length,
If the bits above the corresponding sign bit of input data are assigned as a sign bit area, and the same code data is assigned to each bit in the sign bit area, the code can be recognized no matter which bit in the area is taken in, and the input data can be recognized. You can receive the information contained in the data as is.

Moreover, by expanding the code bit area in this way, processing can be performed by a data processing device having a length of 9 bits to 12 bits.

Conventionally, such code bit expansion has been carried out by a circuit having a configuration as shown in FIG.

That is, in the figure, SR1, SR2, and SR3 are 4-bit shift registers, and each A, B,
C and D are parallel input terminals, QA, QB, QC, and QD are parallel output terminals, and S0 and S1 are control terminals for mode setting. Both control terminals S0 and S1 for this mode setting are at logic level "1"
When , the shift register is in parallel input mode, and when S0 is at logic level "1" and S1 is at logic level "0", it is in shift mode to lower bits.
Also, when S0 is at logic level "0" and S1 is at logic level "1", the mode is set to shift to the upper bit, and both S0 and S1 are at logic level "0".
In each case, the prohibited mode is set.
CLOCK is a clock input terminal, and the operation in each mode is based on this clock input terminal CLOCK.
This is done in synchronization with the clock signal Ck input to the clock. CLEAR is a clear signal input terminal, and when the clear signal Cr is input to this terminal, the shift register is cleared. R is a serial input terminal for lower shift, L is a serial input terminal for upper shift,
Shift register SR1 connects R to its own output terminal QD
, and also shift L to the output terminal QD of shift register SR2.
It is connected to the. In addition, shift register SR2
The serial input terminal R of is connected to the output terminal QA of the shift register SR1, and the serial input terminal L of the shift register SR2 is connected to the output terminal QD of the shift register SR3.
Furthermore, the serial input terminal L of shift register SR3 is grounded, and the serial input terminal R of shift register SR2
They are each connected to the output terminal QA of the bit, forming a bit variable code bit expansion circuit of up to 12 bits in parallel.

In such a circuit, control terminals S0, S1 of each shift register SR1, ~SR3
mode setting signal MOOD1 with logic level “1”,
MOOD2 is applied to set the parallel input mode, and the shift registers are operated in synchronization with the clock signal Ck input to the clock input terminal CLOCK, and the input data applied to the input terminals A and D of each shift register SR1 and ~SR3 are Each shift register SR1,
~ Import it into SR3.

Next, the mode setting signals MOOD1 and MOOD2 are switched to logic levels "1" and "0" in order to shift the mode setting to the upper bits. and,
The entire contents of the shift registers SR1, .about.SR3 are shifted to the upper bits by the clock signal Ck until the designated sign bit of the fetched input data reaches the most significant digit of the shift registers SR1, .about.SR3. At that time, the top shift register
The sign bit is output to the most significant output terminal QD of SR1, and this output is input to the serial input terminal R of the lower shift of shift register SR1.

Therefore, if the mode is set to shift mode to lower bits and the bits are shifted lower by the number of shifts, the highest output terminal QD of the highest shift register SR1 will be connected to the serial input terminal R to shift to the lower bits. This output terminal QD when in shift mode to
Since the data appearing in is retained,
The data output from this circuit in Figure 1, which is composed of three shift registers SR1 and ~SR3, is from the digit position corresponding to the most significant digit of the input data to the most significant digit (MSB) of the most significant digit of the input data. The data is in an expanded form.

Therefore, signed data of any bit length shorter than 12 bits can be converted to signed data of 12 bits.

However, in the case of this method, the data is read in once, shifted upwards by the number of digits insufficient for the final desired bit length, and then shifted downwards again to shift the sign bit to the most significant digit. Therefore, it is necessary to take complicated steps to move the bits to the upper bits.
This method not only requires control for shifting to lower bits, but also has the drawback that the data processing speed is slow due to the above operation.

The present invention was developed in view of the above circumstances, and is a device that expands the sign bit of signed input data and converts it into data with a bit length longer than the bit length of the input data, and supports the bit length of the converted data. It has input terminals with the number of bits, and at least the input terminal corresponding to the sign bit of the input data with the minimum bit length of interest and the input terminals of higher bits are provided with respective gate controls for data input/output. A possible gate is provided between the output sides of the bit corresponding to the sign bit of the input data having the minimum bit length and the respective adjacent bits of higher order bits, and is operated with a gate control signal of opposite polarity to the gate. A gate for transmitting lower bit data is provided to transmit the output of the lower bit side to the upper bit side, and each gate for data input/output is provided with a gate for transmitting the lower bit data, and a gate for transmitting the lower bit data to which the output side is connected to the gate. The configuration is such that a set of gates for transmitting bit data is provided to each gate control signal, and the gate control signal is selected according to the position of the sign bit of the input data, and the bits higher than the bit corresponding to the sign bit of the input data are selected. Close the data input/output gate provided at the input terminal of By closing the lower gate and opening the other gates to transmit the input, the sign bit is extended and converted to data of the required bit length, thereby responding to the sign bit of the input data. The sign bit of the input data can be expanded and outputted by simply applying a control signal to open the gate for input/output of lower-order data, including the bit to be outputted. Therefore, control is easy. It is an object of the present invention to provide a bit-variable code bit expansion circuit which can operate at high speed and has high reliability.

An embodiment of the present invention will be described below with reference to FIG.

In Figure 2, 2-1, 2-2 to 2-8 are the gates of each tri-state, and among these, gates 2-1, 2-2, 2-3, and 2-4 are gate control signals. When the gate control signal is at logic level "1", the input signal is output as is, and when the gate control signal is at logic level "0", the output becomes high impedance.

Furthermore, gate 2-1 is a gate control signal.
It is controlled by Sg4 and controls the passage of the most significant bit (MSB) data bit bit0 output. Also,
Gate 2-2 controls the passage of the output of data bit bit1, and gate 2-3 controls the passage of the output of data bit bit1.
The gates 2-4 control the passage of the outputs of the gates 2 and 2, and the gates 2-4 control the passage of the data bit bit3, respectively.

In addition, the gates 2-5, 2-6, 2-7, 2
-8 has the function of passing the input signal as is when the gate control signal is at logic level "0", and becomes high impedance when the logic level is "1" to block input/output; -1 and 2-2, the gate 2-6 is between the output terminals of the gates 2-2 and 2-3, and the gate 2-7 is between the output terminals of the gates 2-3 and 2-3.
-4, and the gate 2-8 is connected between the output terminal of the gate 2-4 and the data bit bit 4, with the output terminal side being the upper bit side.

Sg1 to Sg4 are gate control signals, respectively. Gate control signal Sg4 is for gates 2-5 as well as gate 2-1, and gate control signal Sg3 is for gates 2-2 and 2-6.
Furthermore, the gate control signal Sg2 controls the gates 2-3 and 2-7, and the gate control signal Sg1 controls the gates 2-4 and 2-8. Bits 5 to 11 are data bits, and bit 11 is the least significant bit (LSB).

This device with such a configuration is capable of handling 8-bit, 9-bit, 10-bit, and 11-bit data if the data packed into the lower bits of the 12-bit data line includes a sign bit in the most significant position. ,12
In either case, the code bit area can be expanded to 12-bit data using the gate control signal, and the specified code can be used regardless of the state of the input signal of the higher-order bits than the specified code bit. Bit “1” or “0”
The code information can be expanded to the most significant bit.

For example, when the input data is 9 bits including the sign bit, the input data is the third upper bit, bit3.
When the 11th bit 11 of the least significant bit is entered, and the third bit 3, which is the most significant bit of the input data, is a sign bit, first, the gate control signal Sg1 for the third bit of the gate control signals Sg1 to Sg4 is input. to logic level “1”,
Further, gate control signals Sg2 to Sg4 for the second to zeroth bits are set to logic level "0".

As a result, gate 2-4 whose gate control input is positive logic and gates 2-7 to 2-5 whose gate control input is negative logic are open, and gates 2-3 to 2-5 whose gate control input is positive logic are open.
Gate 2-1 and gate 2-8 whose gate control inputs are negative logic are closed. Therefore, the code information of the third bit of the input data is transmitted to the output side through the open gate 2-4, and the open gate 2-7 whose input side is connected to this gate 2-4 It is also transmitted to the output side of the second bit bit2. Furthermore, the open gate 2-6 whose input side is connected to the output side of this second bit bit2
It is also transmitted to the output side of the first bit bit1 through
Furthermore, it is also transmitted to the output side of the 0th bit bit0, which is the most significant bit, through the open gate 2-5 whose input side is connected to the output side of the first bit bit1.

At this time, the information on the input side of the 0th to 2nd bits blt0 to bit2 is the information on the input side of the gates 2-1 and 2 in the closed state.
-3 and is not transmitted to the output side, and since the gate 2-8 which receives the output of the fourth bit bit4 as input is in a closed state, this fourth bit bit4 is not transmitted to the output side.
4 output is not transmitted to the output side of the third bit bit3.

In this way, the output data is 12-bit long data by leaving the lower 8 bits of the 9-bit long input data unchanged, and applying the input of the third bit (bit3, which is the sign bit) to the 0th to 3rd bits, bit0 to bit3, respectively. It will be output as

In other words, 9-bit long signed input data is converted to 12-bit long data with the sign bit extended to the upper 4 bits.

Of course, if the input data is signed 8-bit length, by setting each of the gate control signals Sg1 to Sg4 to logic level "0", the fourth bit bit4, which is the most significant bit of the input data, can be set to the logic level "0".
It is possible to expand the coded data of
1 to Sg4, set Sg1 to Sg3 to logic level “1”
By setting Sg4 to the logic level "0", the data from the 1st bit bit1 to the 11th bit bit11 goes directly to the output side, and the input of the 1st bit bit1 further passes through gates 2-5. It is transmitted to the output side of 0 bit bit0 and can be converted into 12-bit length data with the sign bit extended. Similarly, for the configuration shown in Figure 2, 10
It can handle input data up to 12 bits long.

Furthermore, in the circuit according to the present invention, by providing a tri-state gate for each bit starting from the fourth bit 4, it is possible to extend sign bits even to data with a length of 8 bits or less with a sign.
It is also possible to obtain extended code bit data having a bit length or more.

As described above in detail, the present invention provides a device for converting signed input data into data of a desired bit length that is longer than the bit length of the input data by expanding the sign bit, the device having input terminals with a number of bits corresponding to the bit length of the converted data, and providing gate-controllable gates for data input/output at least the input terminal corresponding to the sign bit of input data of a minimum bit length to be targeted and the input terminals for higher bits than this, and providing lower bit data transmission gates between the output sides of the bit corresponding to the sign bit of the input data of the minimum bit length and each of the higher bits that are adjacent to this, which operate with a gate control signal of opposite polarity to the gates and transmit the output of the lower bit side to the higher bit side, and providing each of the data input/output gates with a gate control signal of the same gate and the lower bit data transmission gate whose output side is connected to the gate in question as a pair. Then, by setting the control signal of the bit corresponding to the sign bit of the input data and the lower bits thereof as a signal for opening the gate of the bit, the data input/output gate provided at the input terminal of the bit higher than the bit corresponding to the sign bit of the input data is closed, and among the gates transmitting the output of the lower bits to the output side of the higher bits, the gate lower than the bit corresponding to the sign bit of the input data is closed and the other gates are opened to transmit the input. Therefore, signed input data with a short bit length is extended by transmitting only the sign bit to the higher bits by the number of missing bits, so that it can be converted into signed data of the desired bit length with only the sign bit extended, and when the bit length of the input data is insufficient, In cases where the code bit position is not at the code bit position of the required bit length, for example, by simply controlling the opening and closing of each gate by giving a control signal to open the gate of the bit corresponding to the code bit of the input data, the code bit can be expanded to the more significant bit side to obtain the required bit length.If the data area other than the code bit area is used as input data for a device that knows how many lower bits it has for processing, the original information can be accurately transmitted as signed data.In addition, the control is easier than conventional devices, and since the input is simply transmitted to the output side through an open gate, the code bit can be expanded at high speed.This provides a bit-variable type code bit expansion circuit with excellent reliable characteristics.

The present invention is not limited to the embodiments described above and shown in the drawings, but can be implemented with appropriate modifications within the scope of the invention.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional device, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 2-1, 2-2 to 2-8...gate, bit0,
bit1～bit11...bit, Sg1, Sg2, Sg3,
Sg4...Gate control signal.

Claims (1)

[Scope of utility model registration request] A device for converting signed input data into data with a desired bit length longer than the bit length of the input data by extending the sign bit, has an input terminal with a number of bits corresponding to the bit length of the converted data, and at least Including the input terminal corresponding to the sign bit of the input data with the target minimum bit length, gates that can be controlled for data input/output are provided at the input terminals of bits higher than this, and the minimum bit length is A gate control signal of opposite polarity to the gate is operated between the bit corresponding to the sign bit of the input data and the output sides of the adjacent bits of higher order bits, so that the output of the lower bit side is transferred to the upper bit side. Each gate is provided with a gate for transmitting the lower bit data to be transmitted, and each gate for data input/output is provided with a set of the gate and the gate for transmitting the lower bit data whose output side is connected to the gate. The gate control signal is configured to give a control signal, and the gate control signal is selected according to the position of the sign bit of the input data, and the gate control signal is connected to the input terminal of the bit higher than the bit corresponding to the sign bit of the input data. Also, among the gates that transmit the output of the lower bit side to the output side of the upper bit, the gate lower than the bit corresponding to the sign bit of the input data is closed, and the other gates are open and input. 1. A variable bit type sign bit expansion circuit, which expands the sign bit of input data and outputs the expanded sign bit by transmitting the bit.