SU526905A1 - Device for solving differential equations - Google Patents

Description

one

The invention relates to the field of computer technology and can be used, for example, in the construction of digital computers and digital modeling devices based on large-scale integrated circuits.

A device is known for solving differential equations, containing, its function register, derivative registers, function increment registers, increment derivatives and argument increments, higher derivative register, constant and variable coefficient registers, analysis blocks, the inputs of each of which are connected to the outputs of the corresponding sign trigger. , the outputs of one analysis block are connected to the inputs of the increment register of the function, and the others to the inputs of the corresponding incremental register of derivatives, the control block, the outputs of which th connected to the control inputs of the register increments function registers increments derivatives initial increment register argument, the register increments argument registers permanent and variable ratios and high nroizvodnoy register.

However, the known device does not provide high speed when solving homogeneous linear differential equations, since a considerable part of the solution time is spent on repeatedly accessing the memory device for initial data and intermediate results.

The purpose of the invention is to increase speed when solving homogeneous linear differential equations.

This is achieved by the fact that a switch, a sdvng unit and a block of elements "OR, with registers outputs

the derivative and higher derivative functions are connected to the information inputs of the increment register of the function n registers of increments of derivatives via the shift block, the control inputs of which are connected to the outputs of the switch, the outputs of the latter are connected to the inputs of the corresponding function registers and derivatives and through the block of elements "OR to the input of the register of the highest derivative, and the outputs

constant coefficient registers - to the inputs of the corresponding analysis units. The control inputs of the analysis unit and the control inputs of the switch are connected to the corresponding outputs of the control unit, the output of the initial increment register of the argument is connected to the inputs of the argument increment registers, the outputs of which are connected to the inputs of the corresponding non-temporal coefficient registers, outputs associated with the corresponding

switch inputs. The block diagram of the device shown in the drawing. The uetroystgzo contains m - / - bit register b of increments of the function {/ is an integer determined from the ratio I logzn, t is the size of the nonerans, a is the order of equilibrium), m + par of the increments of lo-bt increments of derivatives, / n + 1-bit register 2i functions, / p- | -1-bit registers 2z-2p derivatives, t- - / - bit register 2 „+1 high derivative, block 3 shift, block 4 elements“ OR, switch 5, / p-bit registers 6i-6 and constant coefficients, triggers 7i-7 and signs, blocks 8i-8 analysis, ml-2-bit register 9i variable coefficient, / nf-1-bit register S Ez-9 and variable coefficients, t-2-bit registers lOj-lOn-i argument increments, t-bit register AND initial increment of the argument and block 12 controls. The function increment register 1, the derivative increment L-In registers and the 2 ½ +1 derivative derivative register have the day of cyclic transfer from the highest order to the least significant, registers 92-9p of variable coefficients - the cyclic shift circuit from the least significant to the preceding one, and register 9i the variable coefficient is a cyclic shift circuit from the previous low to the highest one and a cyclic shift chain from the sub low to the previous low. The outputs of the register li increments of the function are connected to the inputs of the register 2i of the function and through the block 4 of the “ILR1 - with the inputs of the register 2n + i higher derivative, and the outputs of the registers b-Ui of the primary adaptations of the derivatives are connected to the inputs of the registers 22-2 derivatives and through the block 4 elements “OR - to the inputs of the register 2, 4.i, the highest derivative. The outputs of register 2i function, registers 22-2, g derivatives and register 2.1 + 1 higher derivative are connected to the information inputs of the 3-shift unit, and the outputs of the latter to the inputs of the function increment register b and to the inputs of the 2-iji registers of the derivatives. To the control inputs of the shift unit 3, n outputs of the switch 5 and one output of the control unit 12 are connected, the low-order bits of the registers 6i-6p and the outputs of the trigger 7i-7i are connected to the inputs of the 8i-8, g, analysis, respectively. The outputs of block 8i are connected to the control inputs of register Ii, the increments of the function, and the outputs of blocks 82-8p, to the control inputs, respectively, of the increments registers of derivatives. The outputs of the register and the argument increment are brought to the inputs of the registers lOi-lOn-i increments of the argument with a left shift by one bit, and the outputs of the lower bits of the registers lOj- to the control inputs of the registers 92-9 of variable coefficients. The inputs of the switch 5 are connected to the outputs of the lower bits of the registers 92-9p of variable coefficients and with the output of the intermediate format of the register 9i of the variable coefficient, and the corresponding outputs of the control unit 12 are connected to the control inputs of the switchboard. In addition, the outputs of the control unit are connected to the gate inputs of the function increment registers L, derivative increments C-In registers, derivative registers 2 and +1, derivative coefficients 6i-6 registers, analysis registers 8i-8p. 9i-9p variable coefficients, registers lOi -10? -1 increments of the argument and register 11 of the initial increments of the argument. To the inputs of registers 92–9.1 of the non temporary coefficients of the code, the code bus of the control unit in the system with a binary code equal to ((- the index of registers 92–9, g of variable coefficients). The register of increments of function li, the registers of L-1.1 increments of derivatives, the regnstr 2i functions, registers 22-2 of derivatives, the register 2p + 1 of the highest derivative, registers 92-9p of time-constant coefficients and registers of lOi-lOn-i of argument increments have the properties of an adder . The device works as follows. Let it be necessary to solve a homogeneous linear differential equation. . . -f + t / l J - n, f / L na in the interval xo, xi, with given initial conditions mn g / o and g /, where, 2, ..., n-1. In the initial state, the binary code y / o is written to the register 1) increments of the function, and the binary codes y, /, g / (,, ..., - respectively to regnstra 2, 1z, ..., 1 n) n) a1np11Y derivatives, and the posteptels < / RTI > are recorded in the 1FINE code, and negative ones in the reverse. The constant coefficients Co, f / i, ..., a, i 1 are enlarged respectively in registers of GI, 62, ..., 6 "constant coefficients in the direct code, and the reprints of these coefficients are respectively in triggers 7i, Uz , ..., 7n (a positive sign, the sign corresponds to O, and the negative) Pomu-I). Initial increment code LL; the argument is written to register 11 of the initial increment argument, and to register 9) of the variable coefficient, the double Al- code. The remaining device registers are set to zero. When solving an equation, the device operates in three modes: in the mode of calculating variable coefficients; in the calculation mode of the highest derivative; in the function calculation mode. In the nerve mode, variable coefficients are calculated where, 2, ..., n. During the solution of the equation, the calculations in that mode are performed once. For timeout, coeff | n; ienta b, it is necessary to impose n () cycles consisting of two cycles. in the first cycle, the control unit 12 outputs a signal to the control input of the register 11 of the initial increment of the argument and to the input code buses of the registers, i variable coefficients. In this case, in the registers lOi-10 „1, the increments of the argument are summed by the codes of these registers with the code Лх recorded in register 11 and the initial increment of the argument, and the reception of the code A.c to the registers 102, Yuz, ..., of the argument increments is controlled by the lower the bits of the argument increments registers Yu, Yug, ..., Qn-z, respectively, and the reception of the code Dx into the register G1 of the increments of the argument is the younger bit of register 9i of the interchangeable coefficient. In registers 92-9 of the variable coefficients, in the same clock cycle, the contents of these registers are summed with the code-, and the summation process registers the lower bits of the registers lOi-lOn-i. In the second cycle, the right shift of the contents of the registers 9 | -9, g of undiminished coefficients and registers J | -10p-1 of the increments of the argument occurs. When the variable coefficients are shifted in registers 92-9p, the cyclic shift circuit is blocked by the control unit 12, and in the variable coefficient register 9i, the cyclic shift circuit is blocked from the previous minor to the previous one. After performing () i successive cycles, a further shift in each fM register 9i-9p and the variable coefficients (t-index of the register) is not performed, and in each t-th register 10 -IGn-t, the shift stops after (m + l) ( t4-l) successive cycles. After completing the calculations in the first mode, the coefficient codes & i, are recorded respectively in registers 9i, 92, ..., 9p of the variable coefficients. In the second mode, the next value of the highest derivative y, a is calculated. (r-0, 1, ..., kl, where t is n When solving the calculation equation, in this mode, the values are performed / r times, i.e., k times the derivative values of the derivative are sequentially calculated. Before starting the calculations in the second mode, but the signal The control unit 12 transfers cola from register b to assign functions to register 2 | functions and from registers bi-1 of increments of derivatives to registers, derivatives. Then, computation cycles consisting of nL 1 cycles are calculated. in time, it gives control locks 8i-8 ,, an lpza Fni; in tx flip-flops 7) -7n code O is written, and the main bits ix of registers 6i-6n are code 1, then from 1 registers of L-1 „increments of functional increments of the output. x is issuing a direct code. If i-x triggers 7i-7 ,, and in the lower-order bits f-x of the registers 6i-b, g of constant coefficients are written 1, then from / -X registers li-1 ", the function increments and increments of production x are given the reverse code. When O is written in the lower bits of the i-x registers 6i-6 "and the state coefficients, then the code from the g-x registers is -b ,. incremental functions and increments of derivatives are not provided. Register codes b. the increments of the function and the registers L-1 of the increments produced through block 4 of the elements "OR arrive at the inputs of the register 2, j are the highest derivative, where they are summed. In the p-and-th cycle of each cycle, a right shift is performed in register 2 ,, - Li with the highest derivative and in registers 6i-6 ,, with constant coefficients. When shifting in register 2 ,, the highest derivative of the derivative, the lower bits are lost, and in registers 6) -6 ,, of constant coefficients, the lower bits are rewritten in the old reference line along the shift circuit. When the reverse codes are shifted in regreg 2, + i, the highest derivative of the released high order bits are filled with units. After completing the calculation cycles, the code // is written in register 2 ,, -. higher derivative. Then, according to the signal of the control unit 12, the shadow, the register b of the function increments and the registers b.- I ,, the increments hhf are generated, set to the zero state. In the third, the new value of the function at the point .t; ji.r, -4-Ax is calculated using the formula //; j-) /.- + ... Computed in this mode, they are performed k times during the solution time . Initially, the color calculation is calculated // // D.1-Ub, n. It is necessary to carry out t cycles consisting of cycles. In units of block 12, I sequentially issue control signals to the commutator 5 inputs. variable coefficients. When the shift inputs of the signals generated in registers 9i-9, variable coefficients with indices r, are received at the control inputs, the codes of the derivatives registers and the rspstra 2p-h higher derivative, 11th-1x indices; are transferred to the L-7J registers of the function function increments and gtrnranl.oniy derivatives. The indices i -i, where the codes of these registers are summed. V / g + 1-th cycle according to the control unit signal, the right shift of the contents of the register 11 of the functions, the registers L-1 and the derivatives of the registers and the registers 9i-9 of the variable coefficients is carried out. With a code shift in re: pprs 9; Against the coefficient and the vertical shift circuit from the pre-low bit to the highest one is blocked by the control unit 12. In the L register of function increments and the L – In registers of the increments of derivatives, the lower digits are lost during the shift, and the negative digits in the released higher digits are written down. After completing the calculation cycles, the codes of the new increments of the function and the derivatives are recorded respectively in the register 1 of the increments of the function and the registers of the L – U increments of the derivatives. Then, using the control unit signal, the shift register codes 2i and the derivative registers 22-2, respectively, are transferred via the shift unit 3 to the function increment registers li and the derivative increment registers, where the new function and derivatives are generated. After this, the function register 2, the registers 22–2 of the derivatives AND of the register 2 & lt-1 most significant derivative are set to zero, respectively (the zero setting circuit is not shown conventionally in the drawing). Further, the calculations in the second and third modes are repeated until those k until the required values of the function and its derivatives are obtained at the points A, - (, 2, ..., k, respectively).

Claims (1)

Invention Formula A device for solving differential equations containing a register of a function, registers of derivatives, registers of increments of a function, increments of derivatives and increments of an argument, registers of higher derivatives, registers of constant and variable coefficients, blocks of analysis, the inputs of each of which are connected to the outputs of the corresponding trier of the sign The analysis banks are connected to the inputs of the increment register of the function, while others are connected to the inputs of the corresponding register of intermediate operations, the control unit whose outputs are connected ineny to the control inputs of the register increments function registers increments derivatives initial increment register argument, the argument registers increments, registers of constant and variable coefficients and the register of the highest derivative, characterized in that, in order to improve speed when solving homogeneous linear differential equations, A switch, a shift block and a block of OR elements are introduced, the outputs of the function registers of the derivatives and the highest derivative through the shift block, the control inputs of which are connected respectively to the outputs the switch and the control unit are connected to the informational inputs of the increment register of the function and the increment registers of derivatives, the outputs of which are connected to the inputs of the corresponding registers of the function and produced and through the unit of elements OR are connected to the input of the register of the highest derivative, the outputs of the registers of constant coefficients are connected to the inputs of the corresponding analysis units, the control inputs of which and the control inputs of the switch are connected to the corresponding outputs of the control unit, the output of the initial increment register; connected to the inputs of the argument increment registers whose outputs connected to the inputs of the respective registers of variable coefficients, the outputs of which are connected to the corresponding inputs of the switch.