JPS6368941A - Operation monitoring device for cpu - Google Patents

Abstract

PURPOSE:To accurately monitor the operation of a CPU without reference to the configuration of operation abnormality by counting an oscillation output applied to the interruption input of the CPU with an interruption input which can not be masked, and detecting the operation abnormality and initializing the CPU. CONSTITUTION:Every time a pulse signal from an oscillator 13 is applied to the interruption input NMI which can not be masked, the CPU 11 performs interruption processing and also counts the pulse signal to store the result in a memory area 17 of a memory 15 and also store its inverted value in a memory area 19. Then when the interruption processing is performed, it is decided that the memory 15 is destroyed if the inversion contents in the area 17 do not coincide with the contents of the area 19, so that the CPU 1 is initialized. When their coincidence is obtained, on the other hand, it is decided that abnormal operation is performed if the counting contents exceeds a set value 2000, etc., corresponding to single-time interruption processing greatly and reaches a specific value 3000, etc., so that the CPU 1 is initialized. Consequently, the operation of the CPU is accurately monitored irrelevantly to the configuration of the operation abnormality by the simple constitution which requires no timer counter, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a CPU operation monitoring device such as a watchdog timer that monitors an abnormal operation of a central processing unit (CPU).

(Prior Art) Microcomputers are generally provided with a so-called watchdog timer in hardware to monitor abnormalities in the operation of the CPU. FIG. 5 is a diagram showing the outline thereof. In the figure, the counter circuit 101 is connected to the oscillator 103.
For the CPIJ 105, its clear terminal (CL) is connected to a predetermined output terminal (0) of the CPU 105, and its predetermined count output terminal (C10'') is They are respectively connected to the reset terminal (R8T) of the CPU 105. That is, in this circuit, the counter circuit 101
While counting the pulse signals supplied from the oscillator 103, a clear signal, which should be supplied from the CPU 105 at an appropriate timing according to normal operation, is sent to the clear terminal (C
If it is not supplied to the counter circuit 101, it means that some operational abnormality has occurred in the CP[105.
At the same time when the count reaches a predetermined number, a reset signal is supplied to the CPU 105 to return it to the initial state. On the contrary, the CPU
If the counter circuit 105 is in normal operation, the count value of the counter circuit 101 is cleared by a clear signal before reaching the predetermined count number, so that no reset signal is output.

(Problems to be Solved by the Invention) However, the above-described watchdog timer has the following problems. That is, the above-mentioned general circuit is designed on the premise that a clear signal will not be output when an abnormal operation occurs in the CPU 105, so a clear signal is always output when an abnormal operation occurs in the CPU 105. Alternatively, it is impossible to deal with a situation where a clear signal is output extremely irregularly.

The present invention has been made in view of the above, and an object of the present invention is to provide a CPU operation monitoring device that can accurately monitor CPU operation regardless of the type of CPU operation abnormality. be.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention has the following features as shown in FIG.
CPU1 with a non-maskable interrupt input and this C
An oscillation means 3 supplies a signal to the interrupt input of the PUI at an appropriate timing, a count storage means 5 stores the count value of the signal supplied from the oscillation means 3 by the CPLll, and the count value storage means 5 stores the count value of the signal supplied from the oscillation means 3 by the CPLll. An erasing means 7 erases the counted value in the counted value storage means 5 at intervals of a set time longer than the appropriate timing, and an interrupt is activated by a signal supplied to the interrupt input by the oscillation means 3, and the counted value in the counted value storage means 5 is erased. The gist of the present invention is to include an initializing means 9 for detecting the occurrence of an operational abnormality in the CPU based on the above and initializing the CPU.

(Function) The CPU operation monitoring device according to the present invention, especially in a CPU having a non-maskable interrupt input, shifts to forced interrupt processing every time a signal from the oscillation means is supplied to the interrupt input at an appropriate timing. Based on the number of signals supplied from the oscillation means, abnormal operation of the CPU is detected and the CPCI is initialized.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 shows a schematic diagram of a CPU operation monitoring device according to an embodiment of the present invention. In the figure, 11 is a CPU having a non-maskable interrupt input (NMI);
is an oscillator that supplies a pulse signal to this NMI input at an appropriate timing; 15 is connected to CPtJll;
This is a memory that stores the count value of the pulse signal according to 1. That is, in the CPU 11, in addition to the original main program processing, the NMT (described later) is executed by a forced interrupt in conjunction with the supply of pulses to the NMT input at appropriate timings.
It performs MI processing and monitors for operational abnormalities.

Note that the output timing of the pulse signal from the oscillator 13 is shorter than the time when the main program processing is completed, for example, the output timing of the pulse signal from the oscillator 13 is shorter than the time when the main program processing is completed.
The timing is such that 000 pulses are output.

The memory 15 also includes a memory area 1 in which the CPU 11 stores the result of counting the number of pulses supplied from the oscillator 13.
7.19, and memory area 17 has a CPU
11 is stored in the memory area 19 in the memory area h.
The inverted values for the counting results in ili17 are respectively stored. As described in the process described later, by comparing the counted value in the memory area 17 with the value in the memory area 19 after inverting and confirming that they are the same, this prevents data corruption in the memory 15 due to abnormal CPU operation. This is to detect the occurrence.

Next, the operation of this embodiment will be explained using FIGS. 3 and 4. FIG. 3 shows a flowchart of main program processing in the CPU 11, and FIG. 4 shows a flowchart of the NMT processing by forced interrupt in the CPU 11.

In cpuil, after performing initialization processing such as clearing predetermined registers, flags, etc. at the start of operation, it enters main processing and clears the contents of memory area 17.19 of memory 15 when the main processing is completed. After executing the process, the loop returns to the main process and is repeated. (Steps 51-55).

During this main processing (step 53), a pulse signal is supplied from the oscillator 13 to the CPU 11 via the NMI input at an appropriate timing to cause a forced interrupt.
Accompanying this, the NMl process shown in FIG. 4 is performed each time.

In other words, NMI! l! In one theory, first, the value in the memory area 17 is inverted, and then it is determined whether it matches the value in the memory area 19 (step 61). In this judgment process, if a match is detected, the memory 1
If no match is detected, it is determined that the memory 15 has been destroyed due to abnormal operation of the CPU 11, and the process proceeds to step 69, where the CPU 11 is initialized. .

Proceeding to step 63, the contents of the memory area 17 are incremented, and it is determined whether the value has reached a set value (for example, 3000) (step 65). That is, the CPU
If the memory area 11 is operating normally, the memory area 17 is
．． Since the contents of memory areas 17 and 19 should be cleared together, one processing of steps 53 and 55 clears memory areas 17 and 19.
does not exceed 2000, and if it does, it means that some operational abnormality has occurred in the CPU 11 and the process of step 55 is not being performed. Therefore, the contents of memory area 17 are the set value (30
00), the process proceeds to step 69 described above to initialize the CPU 11. Note that if the contents of the memory area 17 do not exceed the set value, a value obtained by inverting the contents of the memory area 17 is newly stored in the memory area 19 for the next NMT process (step 67).

When the above NMI processing is completed, the CPU 11 returns to the main processing (step 53) before the interrupt.

Therefore, according to this embodiment, since the operation of the CPU 11 is monitored by software processing using NMI interrupt input, there is no need to externally connect a counter circuit to the CPU as in the conventional watchdog timer, and the circuit configuration is This reduces the number of components mounted on the board and contributes to compactness.

Note that according to this embodiment, there are two memory areas 17 and 19, and memory corruption is detected by checking the coincidence between the two areas. However, the present invention is not limited to this, for example, both memory areas 1ii! The value in the memory area 19 may be changed so that when the value of 17.19 is added, it always becomes a constant value. Furthermore, the number of memory areas is not limited to two; for example, four memory areas may be provided, two sets of two memory areas may be set, and memory corruption may be detected using the method described above. can be expected to be checked reliably by redundant detection.

[Effects of the Invention] As explained above, according to the present invention, a CPU having a non-maskable interrupt input is used, and each time a signal from the oscillation means is supplied to the interrupt input at an appropriate timing, Moving on to interrupt processing, abnormality in CPU operation is detected based on the number of signals supplied from the oscillation means and the CPU is initialized, so that the CPU operation can be properly monitored regardless of the type of abnormality in CPU operation. can be done.

[Brief explanation of the drawing]

Fig. 1 is a diagram corresponding to claims, Fig. 2 is a diagram showing an overview of an embodiment of the present invention, Figs. 3 and 4 are flowcharts showing the operation of Fig. 1, and Fig. 5 is a general watch. FIG. 2 is a diagram showing an overview of a dog timer. 1... CPU 3... Oscillation means 5
... Count value storage means 7 ... Erasing means 9 ...
- Initialization means 11... CPU 13... Oscillator 15... Memory 17... Memory area 19... Memory area 101... Counter circuit 103... Oscillator 105... CPU

Claims (4)

[Claims] (1) A CPU having a non-maskable interrupt input, an oscillation means that supplies a signal at an appropriate timing to the interrupt input of this CPU, and a count value that stores the count value of the signal supplied from the oscillation means by the CPU. storage means and CPU
During the normal operation of the count value storage means, the count value storage means is activated by an interrupt by an erasing means for erasing the count value in the count value storage means every set time longer than the appropriate timing, and a signal is supplied to the interrupt input by the oscillation means. A CPU characterized by having an initializing means for detecting the occurrence of an operational abnormality in the CPU based on the count value and initializing the CPU.
U operation monitoring device (2) The initialization means detects the occurrence of an abnormality in the operation of the CPU.
2. The CPU operation monitoring device according to claim 1, wherein the CPU operation monitoring device detects when the count value in the count value storage means reaches a set value. (3) The count value storage means has a plurality of areas for storing count values by the CPU, and the initialization means stores the count values based on the comparison result of the plurality of count values to detect the occurrence of an operational abnormality of the CPU. 3. The CPU operation monitoring device according to claim 1, wherein the CPU operation monitoring device detects an abnormality based on the abnormality of the means. (4) The CPU operation monitoring device according to claim 3, wherein the initialization means detects an abnormality in the count value storage means when a plurality of count values are not the same value. .