JPH05108213A - Reset processing circuit by watchdog timer - Google Patents

Abstract

PURPOSE:To leave data when abnormality occurs to check the cause of the abnormality even when a CPU is reset with a reset signal from a watchdog timer by monitoring the operation of software of a computer. CONSTITUTION:This circuit is constituted in such a manner that a CPU reset signal from a watchdog timer circuit 1 is supplied to the non-maskable interruption input terminal of the CPU 3, and also, the reset signal to be supplied to the reset terminal of the CPU 3 is delayed for a prescribed time by a delay circuit 2, and processing to shift the data in a register, etc., when the abnormality occurs to an unerasable area even when the CPU 3 is reset can be performed in non-maskable interruption processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a watch dog used for monitoring the operation of software of computer equipment.
The present invention relates to a reset processing circuit of a central processing unit (CPU) by a timer (WDT; Watch Dog Timer) circuit (monitoring and timing mechanism).

[0002]

2. Description of the Related Art A WDT circuit is a circuit for monitoring the operation of computer software. This circuit is reset at regular intervals during normal operation of software, but if the software does not operate normally for some reason, it will not be reset. This is called a WDT error. When a WDT error occurs, the WDT circuit
A reset signal is given to the PU to initialize the CPU. This is the function of the WDT circuit.

[0003]

However, when such a conventional reset process is performed, the CPU is initialized, so that the WDT left in each register of the CPU and the like.
The information (data) about the error is also erased. This causes a problem that the cause of the WDT error cannot be investigated later. An object of the present invention is to provide a reset processing circuit by a watch dog timer which solves such a problem and can investigate the cause of a WDT error even if it occurs.

[0004]

In the reset processing circuit by the watch dog timer of the present invention, the non-maskable interrupt (NMI: Non Maskable Interrupt) of the CPU is applied to the reset signal line to the CPU from the WDT circuit.
t) In addition to being connected to the input terminal, the reset input terminal of the CPU is connected via a delay circuit. The delay time of the delay circuit is set to be equal to or longer than that time in consideration of the time taken for each data to be taken up by the NMI process of the CPU.

[0005]

The present invention will be described in detail below with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a WDT circuit, 2 is a delay circuit, 3 is a CPU, 4
Is a local bus, 5 to 7 are CPU reset signal lines at the time of WDT error, and 8 is a signal line for resetting WDT.

First, when the software normally operates, W
The WDT circuit 1 is reset through the DT reset signal line 8 at regular intervals (t ₁ seconds). WDT circuit 1
Then, if it is not reset after [t ₁ + t ₂ seconds] (where t ₂ is an arbitrary positive value), a reset signal is sent to the CPU 3. Now, if software malfunctions for some reason and it stops working properly, WDT
If the reset signal to the circuit 1 stops and it is not reset even after [t ₁ + t ₂ seconds] has passed,
A CPU / reset signal is sent. The signal is
It is input to the NMI terminal of the CPU 3 through the signal line 5. C
WD of each register, PC (program counter), SP (stack pointer) in NMI processing of PU3
A process for sucking up data related to T error is performed.

The CPU / reset signal enters the delay circuit 2 via the signal line 6 separately from the signal line 5. After being delayed for a time longer than the time related to the NMI processing of the CPU 3 in this circuit, it is input to the reset terminal of the CPU 3 via the signal line 7.

In this way, even if a WDT error occurs, the CPU will be initialized after detecting the data relating to the error. Further, it is also effective to provide a display device for notifying an operator of software abnormality (WDT error) when a WDT error occurs.

[0009]

As described in detail above, by implementing the present invention, error information (data) can be analyzed even when a WDT error occurs and a CPU reset occurs. Therefore, the WDT can be analyzed. In terms of investigating the cause of an error and managing the product, it is extremely effective in practice.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 WDT circuit 2 Delay circuit 3 CPU 4 Local bus 5-7 Signal line 8 WDT circuit reset signal line

Claims (1)

[Claims] 1. In order to detect data for investigating the cause of abnormal operation of computer software, the operation of computer software is monitored, and when abnormal operation of software is given from a central processing unit via a local bus. When a reset signal is stopped, a watch dog, which outputs a CPU reset signal and supplies it to the non-maskable interrupt input terminal of the central processing unit,
A timer circuit, and an area in which the CPU reset signal from the watch dog timer circuit and the data such as a register in the non-maskable interrupt processing of the central processing unit are not erased even if the central processing unit is reset. A watchdog timer reset processing circuit comprising: a delay circuit for delaying a time longer than the time required for the input to the reset terminal of the central processing unit.