JPS6367817A - Integrated circuit - Google Patents

Abstract

PURPOSE:To detect an abnormal rise in the output voltage of a voltage generating circuit by providing an MOSFET which inputs the potential level on wiring as a gate voltage. CONSTITUTION:The resistance between the drain and source of the MOSFET 11 becomes large and the voltage at an output terminal 12 becomes closer to the ground level (level 0) as a voltage (VCS voltage) which operates a current switching type logic gate (ECL gate), i.e. the voltage on the wiring drops more. As the VCS voltage rises more, on the other hand, the resistance between the drain and source of the MOSFET 11 decreases and the voltage at the output terminal 12 becomes closer to a VEE power source level (level 1). Consequently, when the VCS voltage rises abnormally, the output terminal 12 of the MOSFET 11 is held at the level 1 and the abnormal rise in the VCS voltage is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to integrated circuits, and in particular to MOSFETs.
This invention relates to detecting an abnormal rise in the output voltage of a voltage generating circuit using the following.

[Conventional technology]

FIG. 2 shows the circuit configuration of a general current switching type logic gate (hereinafter referred to as an ECL gate) used in an integrated circuit. 1 is the voltage that operates the ECL gate (hereinafter, ■
2 is a transistor that flows a constant current to the ECL gate by the voltage applied from VCS voltage generation circuit 1, 3 is ■C8 voltage generation circuit 1 and transistor 2, 4.5 is a switching transistor for outputting the logic level of "0"/'''1#, 6 and 7 are output resistors that provide the logic amplitude required by the logic circuit, 8 and 9
is the output terminal, VIN is @* 0 # / @111 #
An input voltage with a logic level of , VREF is a logic level''
a reference voltage with a level intermediate between 0'' and 'l'';
VER is the power supply voltage applied to the integrated circuit, LEE
is the gate current flowing to the ECL gate.

The operation shown in FIG. 2 will be explained below. Note that the following description assumes a negative logic in which the potential level of logic @0'' is greater than the potential level of logic '1''.

The ECL gate receives a current IE determined by the vC8 voltage applied from the VCS voltage generation circuit 1 to the transistor 2.
E flows. When VIN is at a higher voltage than VREF (when VIN is at 10'' level).

4 is an on state, and 5 is an off state. Therefore, the gate current IDE flows through the resistor 6, and the voltage corresponding to the voltage drop of 6 (@1
"level) is output to output terminal 8, and ground level ('"0" level) is output to output terminal 9.VIN
When VIN is at a voltage lower than VREF (when VIN is at the "1" level), 4 becomes an OFF state and 5 becomes an ON state. Therefore, the gate current IEE flows through the resistor 7, and the voltage corresponding to the voltage drop of 7 ("l# level)" is output to the output terminal 9.
A ground level (102 level) is output to the output terminal 8.

Here, the gate current IEEa is determined by the VC8 voltage as described above. That is, the higher the C8 voltage is, the greater the pace-emitter voltage applied to the transistor 2 is, and the IEE increases. Furthermore, the lower the vC8 voltage, the lower the base-emitter voltage applied to the transistor 2, and the lower the IEE. Therefore, if the C8 voltage becomes abnormally high due to temperature changes, the gate current I
EE is very large and may damage circuit elements due to excessive current flow.

[Problem that the invention seeks to solve]

As mentioned above, integrated circuits that use conventional current-switching logic gates as their basic gates have the disadvantage that if the C8 voltage becomes abnormally high, excessive current will flow and damage the integrated circuit itself. Ta.

Compared to the conventional integrated circuit described above, the present invention has an original content in that it can detect that the VC8 voltage has become abnormally high.

[Failure to solve the problem]

The integrated circuit of the present invention includes a MOSFET that receives as a gate voltage the potential level on the wiring connecting the current switching type logic gate that constitutes the integrated circuit and the voltage generation circuit that sets the gate current of the logic gate. have.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, and the difference from FIG. 2 is that a MOSFET is added to input the signal drawn from the wiring 3 to the branch wiring 13 as a gate voltage.

The operation shown in FIG. 1 will be explained below.

■■C8 voltage output from C8 voltage generation circuit 1, that is, voltage on wiring 3 (gate voltage of MO8FET11)
The lower the value, the higher the resistance between the drain and source of the MO8FET 11 becomes, and the voltage at the output terminal 12 becomes closer to the ground level (@Om level).

On the other hand, as the VCS voltage (gate voltage of MO8FET11) increases, the resistance between the drain and source of MO3FET11 becomes lower, and the voltage at the output terminal 12 approaches the VEEil source level ("l# level") K. Therefore, the VO2 voltage becomes abnormal. When the voltage rises to 6vcs, the output terminal 12 of the MO8FET 11 reaches the ``1'' level, and an abnormal rise in voltage is detected.

In the above explanation, the gate electrode of the MO3FET 11 was provided at a position drawn out from the wiring 3 by the branch wiring 113, but the MOSFET is arranged directly under the wiring 3 and uses the wiring 3 itself as the gate electrode without providing a special branch wiring 13. It is clear that the same effect can be expected even if the system is installed.

〔Effect of the invention〕

As explained above, the integrated circuit of the present invention is effective in detecting an abnormal increase in the output voltage of the voltage generating circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram explaining a conventional technique. 1... vC8 voltage generation circuit, 2... transistor for utility current source, 3... VO8 voltage output wiring,
4.5...Switching transistor, 6,7
...Song/output resistance, 8.9...Output terminal, 11
...MOSFET, 12...MOS
Output terminal of FET 11, 13...branch wiring,
G...Ground, VER...Power supply voltage, IEB...Gate current, VIN...
Input voltage, Vl (EF...Reference voltage. Agent Patent attorney Uchihara n EI + Bud l Flash 2nd figure

Claims (1)

[Claims] An MO that inputs the potential level on the wiring connecting the current switching type logic gate that constitutes the integrated circuit and the voltage generation circuit that sets the gate current of the logic gate as the gate voltage.
An integrated circuit comprising an S FET.