JPS6366649A - Control system for execution of instruction in virtual storage mode - Google Patents

Abstract

PURPOSE:To shorten the executing time of an instruction by supplying a clock equal to that of a real storage mode to a processor even in a virtual storage mode when a virtual address indicates a non-paging area. CONSTITUTION:A microprocessor muPC1 sends 0 to a clock control circuit 9 and then transmits the higher and lower bits of a logical address at the fall of the MPU clock. A decoder 10 sends 1 to the circuit 9 in case the higher bits of the logical address sent from the muPC1 are all equal to 0 and a non- paging area is indicated. The circuit 9 sends a clock equal to that of a real storage mode to a multiplexer 4. The multiplexer 4 sends the higher bits of the logical address sent from the muPC1 to the real page address of a register 5. Thus the register 5 sends a real address synthesized from higher and lower bits of the logical address to a main memory. Then the data read out of the register 5 undergo correction of errors through an ECC circuit 7 and are supplied to the muPC1.

Description

[Detailed Description of the Invention] [Summary] In an information processing device that has a real memory mode and a virtual memory mode, while operating in the virtual memory mode, even if the virtual address points to a non-paging area, the same address as in the virtual memory mode is used. It operates in instruction execution time, but since there is no need to convert virtual addresses to real addresses, the same clock as in real memory mode is supplied to the processor in order to save this conversion time.
Reduced instruction execution time.

[Industrial application field]

The present invention relates to an information processing device that can operate in real memory mode and virtual memory mode, and in particular, when operating in virtual memory mode, when a virtual address points to a non-paging area, the instruction execution time is the same as when operating in real memory mode. This invention relates to an instruction execution control method in a virtual memory mode in which the following is achieved.

An information processing device with a virtual memory mode allows programs to use a large address space, but requires a lot of time to convert virtual addresses to real addresses. Therefore, it is desired to shorten the instruction execution time as much as possible in the virtual memory mode.

[Conventional technology]

FIG. 4 is a block diagram illustrating a conventional virtual storage control system.

In this example, assuming that virtual memory is divided into pages and one page is 2 bytes, microprocessor 1 receives a 24-bit logical address (virtual address,
Hereinafter, the most significant bit will be expressed as 223 and the least significant bit will be expressed as 2°). And the upper 13 bits 223 to 21
1 is the logical page address and the lower 11 bits 2 +a~2
° is the address within the page.

This example can operate in both virtual memory mode and real memory mode, and when operating in virtual memory mode, it usually converts logical addresses into real addresses, so as is known, T L is used as hardware. B (Trans
An address translation table TLB 2 composed of a high-speed RAM called a lookaside buffer is used.

This TLB2 has 2048 entries, and is addressed by 11 pins 221 to 211 of the logical page addresses 22'J to 2 of the upper 13 bits. The content of each entry consists of an 11-bit real page address and a 3-bit tag part.

The 3 bits of this tag part are compared with the 1 bit indicating the validity or invalidity of the entry and the 2 bit nod of 2z+, 222 of the logical page address sent by the microprocessor 1, and only when they match, the corresponding entry is It consists of 2 bits to make it valid.

Therefore, the comparator circuit 3 selects 2 z, +, 2 zz of the logical addresses sent out by the microprocessor 1.
The bit and the 2 bits sent from the tag section of TLB 2 match, and 1 bit indicating the validity/invalidity of the tag section indicates the validity of the entry, and the selected TLB
If entry 2 is determined to be valid, the real page address 11 bits 2z is sent from TLB2 via multiplexer 4.
+~2 are sent to the real page address area of register 5, and the intra-page address 11 bits 210~2° sent from microprocessor 1 enter the intra-page address area of register 5, where the 22-bit real address is configured, sent to the main memory 6, and the main memory 6 is accessed.

If this command is a main memory read command that instructs to read data from main memory 6, the data read from main memory 6 is sent to microprocessor 1 after errors are corrected through ECC circuit 7.

The clock control circuit 8 supplies a reference clock necessary for the operation of hardware other than the microprocessor 1 via A, and the microprocessor 1 receives a reference clock from the reference clock depending on whether it is in a virtual memory mode or a real memory mode instructed by the microprocessor 1. The frequency-divided MPU clock is selected and sent out, and a switching signal for the multiplexer 4 is sent out.

FIG. 5 is a time chart in virtual memory mode.

When the virtual memory mode is notified from the microprocessor 1, the clock control circuit 8 immediately operates for 8 cycles of the reference clock from the time the logical address is sent until the data is sent from the main memory 6 to the microprocessor 1. 8τ is required, so the microprocessor 1 sends the MPU clock 8τ after the logical address is sent, and the multiplexer 4
Switch to TL, B2 side.

During this time, as described above (logical addresses 223 to 20 are
2, and T 1. , B read data, there is an undefined state at first, and after a while the data is read out and sent to the multiplexer 4.

Then, as shown in the real address, the TLB read data sent to the real page address area of register 5 is combined with the logical address QIO~2° stored in the in-page address area of register 5, and the A real address of bits is constructed and sent to main memory 6.

Therefore, the data read at the timing shown in the main memory read data is corrected for errors through the ECC circuit 7 and input to the microprocessor 1.

FIG. 6 is a time chart in real storage mode.

When the microprocessor 1 notifies the clock control circuit 8 of the real storage mode, the clock control circuit 8 operates for 6 cycles of the reference clock, that is, 6τ, from when the logical address is sent until the data is sent from the main memory 6 to the microprocessor 1. Since this is necessary, the MPU clock is sent to the microprocessor 1 6τ after the logical address is sent, and the multiplexer 4 is switched to the microprocessor "1" side.

The 24-bit logical address sent by the microprocessor 1 becomes the real address as it is. Multiplexer 4 sends logical addresses 223-21 to the real page address area of register 5. Further, the lower 11 bits 210 to 2° of the logical address sent by the microprocessor 1 are input to the address area within the page of the register 50, and are combined and sent to the main memory 6 as shown in the real address.

Therefore, the data read at the timing shown in the raw data tα read data is input to the microprocessor 1 via the ECC circuit 7.

In the case of FIG. 6, since the time required for the TLB read data shown in FIG. 5 is not required, the microprocessor 1 can read the required data in a time shorter by 2τ.

[Problem that the invention seeks to solve]

As described above, in the virtual memory mode, time is required to access the TLB, so it takes 2τ more time to execute a main memory read instruction than in the real memory mode. However,
Even in the virtual memory mode, there is no need to access the TLB when accessing an area whose address is not translated, that is, a non-paging area.

In this case, as in the real memory mode, the logical address becomes the real address and the main memory is accessed. However, since the clock control circuit selects the MPU clock only by the mode signal instructed by the microprocessor,
Even when TLB access is not required during non-paging 8NM access, there is a problem in that the MPU clock is not supplied to the microprocessor until 8τ has elapsed from the start of the instruction, making it impossible to shorten the instruction execution time.

[Means for solving problems]

In view of these problems, the present invention attempts to control the MPU clock supply so that even in virtual memory mode, when accessing a non-paging area, the instruction execution time is the same as in real memory mode. .

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention.

In FIG. 1, a decoder 10 is added to FIG. 4, and a function is added to the clock control circuit 9 to send out the same MPU clock as in the real storage mode using the output of the decoder 10.

For example, the decoder 10 uses 8 bits from the OK byte of the logical address.
If the space up to the byte is a non-paging area, it detects that logical addresses 223 to 213 are all "0'", sends a non-paging area signal to the clock control circuit 9, and outputs a non-paging area signal to the real memory. The configuration is such that the same 6τ MPU clock as in the mode is sent.

(Function) With the above configuration, even if the decoder 10 is in the virtual memory mode, when accessing a non-paging area, the decoder 10 instructs the clock control circuit 9 to use the same MP as in the real memory mode.
Since the U clock can be supplied to the microprocessor l, the instruction execution time can be shortened.

〔Example〕

In FIG. 1, operations 1 to 7 are similar to those in FIG. 4.

The decoder 10 sends "1" to the clock control circuit 9 when all of the logical addresses 223 to 213 sent by the microprocessor I are "O".

FIG. 2 is a block diagram showing -011 of the clock control circuit 9.

The reference clock is frequency-divided by the divide-by-2 circuit 11, and the frequency is divided by 3/4.
It enters the frequency dividing circuit 12. When in the real memory mode, from the microprocessor 1, '1'' enters the OR circuit 13 from terminal B as a real memory mode signal, and is sent to the multiplexer 4 as a multiplexer switching signal, as well as to the 3/4 frequency divider circuit 12. be done.

Due to the output "1" of the OR circuit 13, the 3/4 frequency divider circuit 12 operates as a 3 frequency divider circuit, and as the MPtJ clock, a clock obtained by dividing the reference clock by 6 together with the 2 frequency divider circuit 11 is sent out. The multiplexer 4 is then switched to the microprocessor 1 side.

Also, when microprocessor 1 is in virtual memory mode, “
O" is input to the OR circuit 13 from the terminal B, and since the output of the OR circuit 13 is "0", the 3/4 frequency divider circuit 12 operates.

Therefore, as the MPU clock, a clock obtained by dividing the base clock by 8 is sent, and the multiplexer 4 outputs the clock from TLB2.
can be switched to the side.

The decoder 10 outputs “1#” as a non-paging area signal.
is input to the OR circuit 13. Therefore, the 3/4 frequency divider circuit 12 operates as a 3 frequency divider circuit, a clock obtained by dividing the reference clock by 6 is sent out as the MPU clock, and the multiplexer 4 is switched to the microprocessor 1 side.

FIG. 3 is a time chart explaining the operation of FIG. 1.

The microprocessor I sends "0" to the terminal B of the clock control circuit 9 shown in FIG. 2, and sends out the logical addresses 223-2 I+ and the logical addresses 210-2 DEG at the falling edge of the MPU clock (2). The decoder 10 sends a "1" to the clocked '4111 circuit 9 as shown in the non-paging area signal.

Therefore, as explained in FIG. 2, the clock control circuit 9
M P Ll clock 6τ after MPU clock ■
is sent instead of ■. The multiplexer 4 is activated by the “1” sent by the clock control circuit 9.
The logical addresses 223-2 are sent to the real page address area of the register 5.

Therefore, as shown in the real address in the register 5, the real address combined with the logical address 210~2° is sent to the main memory 6, and the data successively outputted at the timing shown in the main memory read data passes through the ECC circuit 7. After that, errors are corrected and input to the microprocessor l.

〔Effect of the invention〕

As described above, even in the virtual memory mode, the present invention requires the same instruction execution time as the actual 1a mode when accessing a non-paging area, and can shorten the instruction execution time as a whole.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a circuit showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a clock control circuit, and FIG. 3 is a time chart (-3-4) explaining the operation of FIG. The figure is a block diagram explaining the conventional virtual memory control method, Figure 5 is a time chart in virtual memory mode, and Figure 6 is a block diagram explaining the conventional virtual memory control method.
The figure is a time chart in real storage mode. In the figure, 1 is a microprocessor, 2 is a TLB, 3 is a comparison circuit, 4 is a multiplexer, 5 is a register, 6 is main memory, 7 is an ECC circuit, 8.9 is a clock control circuit, 10 is a decoder, 11 is 2 A frequency dividing circuit, 12 is a 3/4 frequency dividing circuit, and 13 is an OR circuit. Rod 2 ≧ 1 (Q KoC) Shizuku Kai F Upper L Month Moon T Ru Kui Otsu Zu ε Matoi Hikio % Ka question: a-z'r moxibustion 伽 1 meeting p method Σ
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Claims (1)

[Claims] An information processing device having a real memory mode and a virtual memory mode, comprising: a decoder (10) that detects that a virtual address indicates a non-paging area; and a processor (10) using the output of the decoder (10). 1) is provided with a clock control circuit (9) that supplies the same clock as when operating in real memory mode, and even when operating in virtual memory mode, if a virtual address indicates a non-paging area, the processor ( 1)
An instruction execution control method in virtual memory mode characterized by supplying the same clock as in real memory mode.