JPH0535599A - Information processor - Google Patents

Abstract

PURPOSE:To offer the information processor which can read a cache memory at a high speed even when the cache memory is read by using part of a physical address obtained by converting a logical address. CONSTITUTION:The part for reading the cache memory which is the high-order part of the physical address obtained by the last address conversion is stored as an old cache read part OPA(13:12) in a register 14 and the cache memory is read out by using the old cache read part and the offset part LA(11:0) of the logical address while current address conversion is performed. After the address conversion, the new cache read part PA(13:12) and old cache read part OPA(13:12) are compared with each other and the physical address PA(31:14) and a tag address are compared with each other. When those comparison results indicate coincidences, data which are already read out are outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a virtual memory compatible information processing apparatus, and more particularly to an information processing method in which part of a physical address converted from a logical address is used for reading a tag address of a cache memory It relates to the device.

[0002]

2. Description of the Related Art Generally, in a virtual memory system having a cache memory having a physical address tag, an address translation buffer TLB (Translation Lookaside Buffer) is used to convert a logical address into a physical address in order to access the cache memory at high speed. To do. In parallel with this, the entry (tag address and data) of the cache memory is read using the lower part of the logical address that is not translated, that is, the part where the logical address directly corresponds to the physical address (called the offset part). . Then, after the address translation in TLB is completed, T
The physical address obtained by the LB is compared with the tag address read by using a part of the physical address and the offset part of the logical address, and if these addresses match, a cache hit occurs and the cache memory The data that was read at the same time as the tag address is output from. If the above addresses do not match, a cache miss occurs and the external memory device is accessed.

However, this method can be used when the size (page size) of the memory space (page) managed by the TLB is larger than the capacity of the cache memory. That is, this method can be used when the cache memory of the direct map system is larger than the capacity of one set of the cache memory, and when the cache memory of the set associative system is larger than the capacity of one set. it can. If the page size is smaller than the capacity of one set of the cache memory, a part of the physical address other than the offset part will be used to read the entry of the cache memory. Therefore, after the upper part of the logical address is converted to a physical address by TLB, the entry of the cache memory is read using the address that combines the lower bits of the converted physical address and the offset part of the logical address. Become. Then, the read tag address is compared with the upper part of the physical address to determine a cache hit or cache miss.

FIG. 4 shows a schematic block diagram of an example of the conventional information processing apparatus. The information processing apparatus shown in FIG. 4 has a central processing unit 1, a TLB 2 for converting the upper 20 bits of a 32-bit logical address generated by the central processing unit 1 into the upper 20 bits of a 32-bit physical address, and a direct map method. It has a cache memory 3. TLB2
Is a logical address storage unit 2 for storing logical addresses
1 and a physical address storage unit 22 for storing the physical address corresponding to each logical address. The direct map cache memory 3 includes a decoder 31, a tag unit 32 that stores a tag address, a data unit 33, a comparator 34, and a tristate buffer 35.
And have.

In the information processing apparatus shown in FIG. 4, the memory space is divided into pages of 4096 bytes (2 12 bytes: usually called 4 Kbytes) for management.
The lower 12 bits of the logical address are the offset part.
Assuming that the capacity of the cache memory 3 is 16 Kbytes (2 14 bytes), the tag address is determined to be 18 bits (32-14 = 18).
The lower 14 bits of the physical address are used to read the entry.

An access operation of the cache memory 3 in the information processing apparatus having the above configuration will be described.
First, the upper 20 bits LA (31: of the 32-bit logical address LA (31: 0) generated by the central processing unit 1
12) TLB2, PA of upper 20 bits of physical address
Convert to (31:12). Then, the lower 2 bits PA (13:12) of the converted physical address and the lower 12 bits LA (12: 0) of the logical address are combined 14
The entry of the cache memory 3 is read using the bit signal. Specifically, the 14-bit signal is decoded by the decoder 31 to read the tag address from the tag section 32 and the data from the data section 33 of the selected entry, respectively. Next, after the address conversion in TLB2 is completed, the comparator 34 compares the read tag address with the upper 18 bits PA (31:14) of the physical address, and if they match, a cache hit occurs. The data previously read from the data section 33 is output via the tri-state buffer 35.
If they do not match, a cache miss occurs and the external memory device is accessed.

[0007]

However, in the above configuration, after the conversion of the logical address into the physical address is completed by the address translation device 2, a part of the translated physical address is read out from the entry of the cache memory. Therefore, there is a problem that the reading of the entry of the cache memory 3 cannot be started until the address conversion in the address conversion device 2 is completed, and the reading of the cache memory 3 becomes slow.

In view of the above problems, the present invention provides information that can be read at high speed even when a part of a physical address obtained by translating a logical address is used for reading an entry in a cache memory. An object is to provide a processing device.

[0009]

In order to achieve the above object, the invention of claim 1 reads a cache memory of an upper part of a physical address obtained by address conversion of an upper part of a previous logical address. Is stored in the register as the old cache read unit, and at the same time the next address conversion is performed, the entry of the cache memory is read by the old cache read unit and the logical address offset unit, and the physical address upper part obtained by the address conversion is If the cache read unit is the same as the old cache read unit, the data of the already read entry is used as the read data.

Specifically, a solution means taken by the invention of claim 1 is a central processing unit for generating a logical address and a cache memory of a direct map system or a set associative system for storing an entry consisting of a tag address and data. An address translation device for translating the upper part of the logical address into a physical address upper part, and an old address used in the reading of the cache memory in the physical address upper part obtained by the previous address conversion in the address translation device. A register for storing the cache reading unit,
The old cache reading unit stored in the register is provided with a comparing unit for comparing the old cache reading unit stored in the register with the new cache reading unit of the physical address upper part obtained by the address translation device. When an entry is read from the cache memory by an offset part composed of a lower part of the logical address which is not subjected to address translation, and the comparison means detects that the old cache read part and the new cache read part match. The data read by the cache memory is used as read data, and when it is detected that they do not match, the new cache read unit of the physical address upper part obtained by the address translation device is stored in the register. The contents of the register and the above The offset portion of the address is to a configuration in which the data read out data entry read from said cache memory.

According to a second aspect of the present invention, in the first aspect of the invention, the comparing unit detects that the old cache reading unit and the new cache reading unit match each other, and the physical address obtained by the address translation device. When the upper part matches the tag address of the already read entry, the data of the already read entry is output at the same time as the tag address. Specifically, in the invention of claim 1, the comparison unit detects that the old cache read unit and the new cache read unit match each other, and the tag address of the entry read from the cache memory. Reading the entry read from the cache memory by the old cache read unit and the logical address offset unit stored in the register when the physical address upper part obtained by the address translation device matches. The data output means for outputting data is further added.

Further, in the invention of claim 3 according to the invention of claim 1, when the comparing means detects that the old cache read part and the new cache read part do not match, the physical conversion obtained by the address translation device. The processing of the central processing unit is temporarily stopped while the new cache reading unit in the upper address section is stored in the register. Specifically, in the invention of claim 1, when the comparison unit detects that the old cache reading unit and the new cache reading unit do not match, the central processing unit of the central processing unit is operated for the next one cycle. A holding request means for requesting the central processing unit to hold the state is further added.

According to a fourth aspect of the present invention, the address translator is provided with a plurality of address translators respectively corresponding to the values of the upper portion of the logical address used for reading the cache memory, and the upper portion of the logical address is input. At this time, the entry of the cache memory is read by the hit signal output from the corresponding address conversion section and the offset section of the logical address.

Specifically, a solution means taken by the invention of claim 4 is a central processing unit for generating a logical address and a cache of a direct map system or a set associative system in which an entry composed of a tag address and data is stored. A memory, an address translation device for translating the upper part of the logical address into a physical address upper part, and a value of a cache read part used for reading the upper part of the logical address of the cache memory, which constitutes the address translation device. A plurality of address conversion units that output a hit signal when a higher-order part of the logical address including the corresponding cache read unit is input, and any one of the plurality of address conversion units is provided. OFF consisting of the hit signal and the lower part of the logical address that is not translated By the Tsu preparative portion in which a structure in which entries are stored in the cache memory is read.

According to the invention of claim 5, in the invention of claim 4, a plurality of entries of the cache memory are selected by the offset part of the logical address, and the address translation part is selected from the selected plurality of entries. One entry is selected based on a hit signal from any one. Specifically, according to the invention of claim 4, based on a hit signal from any one of the first entry selecting means for selecting a plurality of entries of the cache memory by the offset part of the logical address, and a hit signal from any of the address conversion parts. And a second entry selecting means for selecting one of the plurality of entries selected by the first entry selecting means.

According to a sixth aspect of the invention, a portion for storing read information of the entry stored in the cache memory is provided in the address translation device, and the entry corresponding to the physical address upper part obtained by the address translation device is the cache memory. If the read information is stored in the cache memory, the read information is output, and the entry of the cache memory is read by the read information and the offset portion of the logical address.

Specifically, a solution means taken by the invention of claim 6 is a central processing unit for generating a logical address and a cache of a direct map system or a set associative system in which an entry composed of a tag address and data is stored. A memory, an address translation device that translates the upper part of the logical address into a physical address upper part, and read information of an entry provided in the address translation device and stored in the cache memory is stored and obtained by the address translation device. A read information storage unit that outputs the read information when an entry corresponding to the upper physical address portion stored in the cache memory is stored in the cache memory, and the read information from the read information storage unit and the logic that is not address-converted. With the offset part consisting of the lower part of the address, the key Entry Sshumemori the stored one in which is configured to be read out.

According to the invention of claim 7, in the invention of claim 6, a plurality of entries of the cache memory are selected by the offset part of the logical address, and based on the read information from the selected plurality of entries. To select one entry. Specifically, according to the invention of claim 6, based on the first entry selecting means for selecting a plurality of entries of the cache memory by the offset part of the logical address, and the read information from the read information storage part. The second entry selecting means for selecting one of the plurality of entries selected by the first entry selecting means is further added.

[0019]

According to the structure of the first aspect of the present invention, the portion for reading the cache memory of the upper portion of the physical address obtained by address-converting the upper portion of the previous logical address is stored in the register as the old cache reading portion. Therefore, the entry in the cache memory can be read by the old cache reading unit and the logical address offset unit during the next address conversion.
Next, after the address conversion is completed, the new cache read unit and the old cache read unit of the physical address upper part obtained by the address conversion are compared, and if the old and new cache read units match, the already read The data of the selected entry is used as the read data and the processing is continued as it is. Therefore, the cache memory can be accessed before the address conversion of the logical address is completed, and the access time of the cache memory can be shortened. As described above, the invention of claim 1 uses the continuity of the program that the cache read unit of the physical address upper part often matches the previous cache read unit of the physical address upper part, and thus reads the cache memory. It saves time.

According to the configuration of the second aspect of the present invention, it is detected that the old and new cache read units match, and the tag address of the entry read from the cache memory and the physical address obtained by the address translation device. When the address upper part matches, the read data of the already read entry is output from the data output means, so that the read time of the cache memory can be shortened.

According to the third aspect of the present invention, when it is detected that the old and new cache read units do not match, the holding request means requests the central processing unit to hold the state of the central processing unit. Is output to the cache memory in the next cycle.
Processing can be continued simply by wasting cycles. Therefore, the processing speed of the information processing device hardly decreases.

According to the structure of the invention of claim 4, the address translation device is provided with a plurality of address translation units respectively corresponding to the values of the read unit of the cache memory in the upper portion of the logical address, and the upper portion of the logical address is input. If the corresponding data is present in the cache memory at the time, the hit signal is output from the corresponding address conversion unit. By reading the entry of the cache memory by this hit signal and the offset part of the logical address, the reading of the entry of the cache memory can be started without waiting for the end of the address translation in the address translator. As a result, the read time of the cache memory can be shortened. Further, since the address translation device is composed of a plurality of address translation parts, it is possible to detect a cache hit in the address translation device at a higher speed than in the case where it is not composed of a plurality of address translation parts.

According to the configuration of the invention of claim 5, the first
Of the plurality of entries selected by the first entry selecting means by the second entry selecting means on the basis of a hit signal from any of the address conversion units. Since one of the two is selected, the read time of the cache memory is shortened.

According to the configuration of the sixth aspect of the present invention, the read information storage unit in which the read information of the entry stored in the cache memory is stored is provided in the address translation device, and the logical address input to the address translation device is provided. When the corresponding corresponding entry is stored in the cache memory, the read information of the entry is output from the read information storage unit, so that the entry of the cache memory can be read without waiting for the completion of the address translation in the address translation device. You can start. Therefore, the read time of the cache memory is shortened.

According to the structure of the invention of claim 7, the first
The plurality of entries of the cache memory are selected by the entry selection means of the first entry selection means, and the first entry selection means selects the first entry based on the read information from the read information storage section.
Since one of the plurality of entries selected by the entry selecting means is selected, the read time of the cache memory is shortened.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration diagram of an information processing apparatus according to a first embodiment of the present invention. The information processing apparatus of the present embodiment includes a central processing unit 1 and a TLB (address translation buffer) 2 of a full associative method for translating an upper part of a logical address generated by the central processing unit 1 into an upper part of a physical address. , And a direct map type cache memory 3. The TLB 2 has a logical address storage unit 21 and a physical address storage unit 22 that stores a physical address corresponding to each logical address. The logical address storage unit 21 is composed of an associative memory (CAM), and the physical address storage unit 22 is composed of a random access memory (RAM). In addition, the cache memory 3 of the direct map type has a decoder 31
The tag unit 32, the data unit 33, the comparator 34, and the tri-state buffer 35.
A part of the physical address is stored in the tag part 32, and the data to be read is stored in the data part 33. Further, in the information processing apparatus of the present embodiment, the cache reading unit used for reading the entry (tag and data) of the cache memory in the physical address upper part obtained in the previous address conversion in TLB2 is the old cache reading unit. 14 for storing as
Old cache read unit and this TL stored in
When a match is detected by the comparator 5 that compares the new cache read unit of the higher physical address obtained by the address conversion in B2, and the comparator 34 and the comparator 5, "
It has an AND gate 16 that outputs H (HIGH) "and an inverter 7 that makes a wait request to the central processing unit 1 when the comparator 5 detects a mismatch. , AND gate 16 and tri-state buffer 35 constitute data output means.

In this embodiment, it is assumed that both the logical address space and the physical address space are 4 Gbytes, and the address space (memory space) is managed by 4 Kbyte pages. Therefore, the logical address generated by the central processing unit 1 is 32 bits, the upper 20 bits of the logical address are translated into the upper 20 bits of the physical address in the TLB 2, and the lower 12 bits of the logical address are the lower bits of the physical address as they are. It is used as 12 bits (offset part). The capacity of the cache memory 3 is 16 Kbytes.

A read operation of the cache memory 3 in the information processing apparatus having the above configuration will be described with reference to FIG. First, the upper 20 bits LA of the logical address LA (31: 0) generated by the central processing unit 1
TLB2 is accessed by (31:12). T
The LB 2 searches for a matching logical address in the logical address storage unit 21, and if there is a matching logical address, the physical address storage unit 22 stores the logical address LA.
The upper 20 bits PA (31:12) of the physical address corresponding to (31:12) are read. If there is no matching logical address, the address conversion is performed by referring to the table in the main memory, and the address is registered in TLB2. Further, in parallel with the address conversion in the TLB 2, reading of the cache memory 3, that is, reading of the tag address stored in the tag unit 32 of the cache memory 3 and the data stored in the data unit 33 is performed. . The cache memory 3 is read by the PA that is the cache read unit of the physical address obtained by the previous address conversion.
Using 14 bits, which is the sum of the output OPA (13:12) of the register 14 that stores (13:12) as the old cache read unit and the lower 12 bits LA (11: 0) of the current logical address. Done. That is, the 14
By inputting the bit address data to the decoder 31, the tag address (the upper 18 bits of the physical address) is read from the tag unit 32 and the data is read from the data unit 33.

Next, after the address translation in TLB2 is completed, the old cache read unit OPA (13: 1) stored in the register 14 and obtained by the previous address translation.
The comparator 5 compares 2) with the new cache read unit PA (13:12) obtained by the current address conversion. Further, the comparator 34 compares the tag address TA read in parallel with the high-order 18-bit PA (31:14) of the physical address converted by the TLB2. The comparator 5 detects that the old cache read unit and the new cache read unit match, and the comparator 34 matches the tag address TA with the upper 18 bits PA (31:14) of the physical address. If it is detected that the data is present, the data of the entry already read from the cache memory 3 is output as the read data.
That is, when a match is detected by the comparator 5 and the comparator 34, a cache hit occurs and the output of the AND gate 16 becomes "H". As a result, the data previously read from the data section 33 is output via the tri-state buffer 35. When the reading of the cache memory 3 is completed in the register 14, the new cache reading unit PA (13:12) of the physical address obtained by the address conversion in the TLB 2 is set to the next cache memory 3
Is written as the old cache reading unit in the reading of.

On the other hand, in the comparator 5, the old cache read unit OPA (13:12) and the new cache read unit PA are used.
AND when the match with (13:12) is detected and the comparator 34 detects a mismatch between the physical address PA (31:14) and the tag address TA, that is, when a cache miss is detected. The output of the gate 16 is "L (LO
W) ”. This causes the external memory to be accessed. Further, when the comparator 5 detects a mismatch, a wait signal is sent to the central processing unit 1 via the inverter 7. This wait signal The received central processing unit 1 is
It is controlled to maintain the current state for the next one cycle. In the cycle in which the state of the central processing unit 1 is held, that is, in the next cycle in which the mismatch between the old and new cache read units is detected, the new cache read unit of the physical address already written in the register 14 is used again. Reading of the cache memory 3 is performed.

As described above, according to the information processing apparatus of the present embodiment, the entry of the cache memory 3 is read by using the old cache read unit obtained by the previous address conversion and the logical address offset unit. Because it will be
The tag and data in the cache memory can be read without waiting for the completion of the address conversion from the logical address to the physical address. Next, when the address translation in the address translation device 2 is completed, the old cache reading section used for reading the entry of the cache memory 3 is compared with the cache reading section of the physical address obtained by the address translation, and if they match, Since the processing can be continued as it is, the read time of the cache memory 3 is shortened. Such shortening of the read time utilizes the continuity of the program that a part of the physical address often coincides with a part of the previous physical address. In the present embodiment, even if the old and new cache read units do not match, by reading the cache memory 3 in the next cycle, it is possible to waste time in one cycle. Therefore, the processing speed of the information processing device hardly decreases.

FIG. 2 shows the schematic arrangement of an information processing apparatus according to the second embodiment of the present invention. The information processing apparatus of this embodiment is
It has a central processing unit 1, a TLB 4 of a full associative system for converting an upper part of a logical address generated by the central processing unit 1 into an upper part of a physical address, and a cache memory 3 of a direct map system.

The TLB 4 has a logical address storage unit 41,
The physical address storage unit 42 stores the physical address corresponding to each logical address. The logical address storage unit 41 is composed of an associative memory (CAM), and the physical address storage unit 42 is composed of a random access memory (RAM). Also, TLB4
Are four address translation units 4a, 4b, corresponding to the values of the cache read unit used to read the entry of the cache memory among the stored physical addresses.
It is divided into 4c and 4d. The logical address corresponding to the address conversion unit 4a is the cache read unit PA (1
3:12) corresponds to the physical address whose value is “0”,
The logical address corresponding to the address conversion unit 4b corresponds to the physical address whose value in the cache read unit PA (13:12) is "1", and the logical address corresponding to the address conversion unit 4c is the cache read unit PA (13:12). 12)
Corresponds to the physical address whose value is "2", and the logical address corresponding to the address conversion unit 4d corresponds to the physical address whose value of the cache read unit PA (13:12) is "3". Each of the address conversion units 4a to 4d detects whether or not there is a logical address that matches the input logical address, and hits from the address conversion units 4a to 4d in which it is detected that there is a corresponding physical address. Signals CAMH0, CAMH1, CAMH2
CAMH3 is output.

The direct map type cache memory 3 has a decoder 36 as a first entry selecting means.
An entry selection circuit 37 as a second entry selection means, a tag section 32, a data section 33, and a comparator 34.
And a tri-state buffer 35. A part of the physical address is stored in the tag part 32,
The data section 33 stores the data to be read. The decoder 36 outputs a signal for selecting four entries based on the offset portion of the input logical address, and the entry selection circuit 37 hits from the address conversion units 4a to 4d among the signals for selecting these four entries. Signals CAMH0, CAMH1, CAMH2, CAMH
Select one entry based on 3.

In this embodiment, both the logical address space and the physical address space are 4 Gbytes, and the address space (memory space) is assumed to be managed by 4 Kbyte pages. Therefore, the logical address generated by the central processing unit 1 is 32 bits, the upper 20 bits of the logical address are translated into the upper 20 bits of the physical address in the TLB 2, and the lower 12 bits of the logical address are the lower bits of the physical address as they are. It is used as 12 bits (offset part). The capacity of the cache memory 3 is 16 Kbytes.

A read operation of the cache memory 3 in the information processing apparatus having the above configuration will be described with reference to FIG. First, the upper 20 bits LA of the logical address LA (31: 0) generated by the central processing unit 1
TLB 4 is accessed by (31:12). T
The LB 4 searches whether there is a matching logical address in the logical address storage unit 41 of each of the address conversion units 4a to 4d. The matching logical address is the address translation unit 4a.
If it is in the address conversion unit 4b, the hit signal CAMH0 is output, if it is in the address conversion unit 4b, the hit signal CAMH1 is output, and if it is in the address conversion unit 4c, the hit signal CAMH is output.
2 is output, and if it is in the address conversion unit 4d, the hit signal CAMH3 is output. Next, the upper 20 bits PA of the corresponding physical address from the physical address storage unit 42
(31:12) is read. If there is no matching logical address in any of the address conversion units, the address conversion is performed by referring to the table in the main storage device.
Register in B4. Further, in parallel with the conversion of the logical address in the TLB 4, reading of the cache memory 3, that is,
The tag address stored in the tag unit 32 of the cache memory 3 and the data stored in the data unit 33 are read. To read the cache memory 3,
First, the lower 12 bits LA (11: 0) of the logical address are used. By inputting LA (11: 0) to the decoder 36, a signal for selecting four entries is selected. If there is a matching logical address in any of the address translation units 4a to 4d in the address translation device 4, the hit signals CAMH0, CAMH1, CAMH2,
Any of CAMH3 becomes "H", and the entry selection circuit 37 selects the entry to be read. Then, the tag address (the upper 18 bits of the physical address) is read from the tag unit 32 and the data is read from the data unit 33.

Next, after the address translation in TLB4 is completed, the read tag address TA and the upper 18 bits P of the physical address obtained by the address translation in TLB4
A (31:14) is compared by the comparator 34. When the comparator 34 detects that the tag address TA and PA (31:14) match each other, a cache hit occurs, and the data previously read from the data unit 33 passes through the tri-state buffer 35. Is output. When the comparator 34 detects that the tag address TA and PA (31:14) do not match, a cache miss occurs and the external memory is accessed.

As described above, according to the information processing apparatus of the present embodiment, the entry of the cache memory 3 is read by the hit signal from each of the divided address conversion units 4a to 4d of the address conversion apparatus 4, so that the address is read. The reading of the entry of the cache memory 3 can be started without waiting for the completion of the conversion of the logical address into the physical address in the conversion device 4, and the read time of the cache memory 3 is shortened. Further, since the address translation device 4 is divided into four address translation units 4a to 4d and used, the address translation device 4 can detect the matching logical address at a higher speed than in the case where the address translation device 4 is not divided and used. it can.

FIG. 3 shows the schematic arrangement of an information processing apparatus according to the third embodiment of the present invention. The information processing apparatus of this embodiment is
It has a central processing unit 1, a TLB 6 of a full associative system for converting an upper part of a logical address generated by the central processing unit 1 into an upper part of a physical address, and a cache memory 3 of a direct map system.

The TLB 6 has a logical address storage unit 61,
The physical address storage unit 62 stores physical addresses corresponding to the respective logical addresses, and the read information storage unit 63 stores read information of the entries stored in the cache memory 3. Logical address storage unit 6
1 is composed of an associative memory (CAM), and the physical address storage unit 62 is composed of a random access memory (RAM). The read information storage unit 63 is RA
When the logical address storage unit 61 detects that the entry corresponding to the logical address is stored in the cache memory 3, the read information DA0, DA1, DA2, DA3 of the entry is immediately output. Is configured. Such a configuration of the read information storage unit 63 is realized by a method in which the sense line for detecting the match in the associative memory (CAM) and the word line of the RAM of the physical address storage unit 62 are made common.

The direct map type cache memory 3 has a decoder 36 as a first entry selecting means.
An entry selection circuit 37 as a second entry selection means, a tag section 32, a data section 33, and a comparator 34.
And a tri-state buffer 35. A part of the physical address is stored in the tag part 32,
The data section 33 stores the data to be read. The decoder 36 outputs a signal for selecting four entries on the basis of the offset portion of the input logical address, and the entry selection circuit 37 reads the read information from the read information storage unit 63 among the signals for selecting the four entries. One entry is selected based on DA0, DA1, DA2, DA3.

In this embodiment, both the logical address space and the physical address space are 4 Gbytes, and the address space (memory space) is assumed to be managed by 4 Kbyte pages. Therefore, the logical address generated by the central processing unit 1 is 32 bits, the upper 20 bits of the logical address are translated into the upper 20 bits of the physical address in the TLB 2, and the lower 12 bits of the logical address are the lower bits of the physical address as they are. It is used as 12 bits (offset part). The capacity of the cache memory 3 is 16 Kbytes.

A read operation of the cache memory 3 in the information processing apparatus having the above configuration will be described with reference to FIG. First, the upper 20 bits LA of the logical address LA (31: 0) generated by the central processing unit 1
The TLB 6 is accessed by (31:12). T
The LB 6 searches the logical address storage 61 for a matching logical address. If there is a matching logical address in the logical address storage unit 61, the upper 20 bits P of the corresponding physical address from the physical address storage unit 62
A (31:12) is read. If there is no matching logical address, the address conversion is performed by referring to the table in the main memory, and the address is registered in the TLB 6. TLB
The cache memory 3 is also read in parallel with the conversion of the logical address in 6.

The reading of the tag address and the data of the entry of the cache memory 3 is first performed by the lower 12 bits LA (11: 0) which is the offset part of the logical address. By inputting LA (11: 0) to the decoder 31, a signal for selecting four entries is selected. If there is a matching logical address in the logical address storage unit 61 in the address translation device 6, the read information D of the entry to be selected from the read information storage unit 63.
A0, DA1, DA2, DA3 are output, and the entry to be read is selected by the entry selection circuit 37 based on the read information. Next, the tag address (upper 18 bits of the physical address) from the tag unit 32 is transferred to the data unit 3
The data is read from -3.

Next, after the address translation in TLB6 is completed, the read tag address TA and the upper 18 bits P of the physical address obtained by the address translation in TLB6
A (31:14) is compared by the comparator 34. When the comparator 34 detects that the tag address TA and PA (31:14) match each other, a cache hit occurs, and the data previously read from the data unit 33 passes through the tri-state buffer 35. Is output. When the comparator 34 detects that the tag address TA and PA (31:14) do not match, a cache miss occurs and the external memory is accessed.

As described above, according to the information processing apparatus of this embodiment, when the address translator 6 detects a matching logical address, the read information for selecting the entry to be read from the cache memory 3 is immediately read out. Since the information is output from the information storage unit 63, the reading of the entry in the cache memory 3 can be started without waiting for the end of the conversion of the logical address into the physical address in the address translation device 6. As a result, the read time of the cache memory 3 is shortened.

[0047]

As described above, in the information processing apparatus according to the first aspect of the invention, the continuity of the program is used to store the old cache read section and the logical address offset section stored in the register. The entry of the cache memory is read during the next address conversion, and the new and old cache read units are compared after the address conversion. If the old and new cache read units match, the data of the already read entry can be used as read data, and the processing can continue. Therefore, even when the cache read unit of the physical address is used to read the cache memory entry, the read time Can be shortened.

Further, in the information processing apparatus according to the second aspect of the present invention, it is detected that the old and new cache read units match, and the tag address of the entry read from the cache memory and the address translation unit obtain the tag address. When it is detected that the upper part of the physical address that has been read matches, the data of the entry that has already been read is output as read data from the data output means. The read time can also be shortened when used to read the memory entry.

Further, in the information processing apparatus according to the third aspect of the present invention, when it is detected that the old and new cache read units do not match, a request for holding the state of the central processing unit is issued by the holding request means. Since the data is output to the central processing unit, the cache memory is read in the next cycle, so that the processing can be continued by wasting only one cycle. Therefore, the processing speed of the information processing device hardly decreases.

In the information processing apparatus according to the fourth aspect of the present invention, the address translation apparatus is provided with a plurality of address translation sections, and when the upper portion of the logical address is input, a hit signal from the corresponding address translation section is input. Is output, the cache memory entry is read by this hit signal and the logical address offset portion, so that the reading of the cache memory entry can be started without waiting for the end of the address translation in the address translation device. it can. Therefore, the read time of the cache memory can be shortened. Further, since the address translation device is composed of a plurality of address translation units,
It is possible to detect a cache hit in the address translation device at a higher speed than in the case where it is not composed of a plurality of address translation units.

In the information processing apparatus according to the fifth aspect of the present invention, the plurality of entries in the cache memory are selected by the first entry selecting means, and the second entry is selected based on the hit signal from any of the address conversion units. Since the selecting unit selects one of the plurality of entries selected by the first entry selecting unit, it is possible to shorten the read time of the cache memory.

In the information processing apparatus according to the sixth aspect of the present invention, the read information storage unit for storing the read information of the entry of the cache memory is provided in the address translation device, and the logical address input to the address translation device is provided. When the corresponding entry is stored in the cache memory, the read information of the entry is output from the read information storage unit, so that the reading of the entry in the cache memory is started without waiting for the end of the address translation in the address translation device. Therefore, the read time of the cache memory can be shortened.

Further, in the information processing apparatus according to the invention of claim 7, the plurality of entries of the cache memory are selected by the first entry selecting means, and the second entry is selected based on the read information from the read information storage section. Since the selecting unit selects one of the plurality of entries selected by the first entry selecting unit, it is possible to shorten the read time of the cache memory.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an information processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of an information processing apparatus according to a second embodiment of the present invention.

FIG. 3 is a schematic configuration diagram of an information processing apparatus according to a third embodiment of the present invention.

FIG. 4 is a schematic configuration diagram of a conventional information processing device.

[Explanation of symbols]

1 central processing unit 2, 4, 6 TLB (address conversion buffer) 4a, 4b, 4c, 4d address conversion unit 3 cache memory 5, 34 comparator 7 inverter (holding request means) 14 register 16 AND gates 21, 41, 61 Logical address storage units 22, 42, 62 Physical address storage units 31, 36 Decoder (first entry selection unit) 32 Tag unit 33 Data unit 35 Tristate buffer 37 Entry selection circuit (Second entry selection unit) 63 Read information Storage

Claims (7)

[Claims] 1. A central processing unit for generating a logical address, a cache memory of a direct map system or a set associative system for storing an entry consisting of a tag address and data, and a higher part of the logical address is a physical address upper part. An address translation device that translates to a register, a register that stores the old cache read unit that is in the upper part of the physical address obtained by the previous address translation in the address translation device, and that is used to read the cache memory, and the register that stores it. The old cache read unit stored in the register is not translated from the old cache read unit stored in the register. The lower part of the logical address The data read by the cache memory is read when the entry is read from the cache memory by the fusing unit and the comparison unit detects that the old cache reading unit and the new cache reading unit match. When it is detected that they do not match, after the new cache read unit of the physical address upper part obtained by the address translation device is stored in the register,
An information processing apparatus configured to use, as read data, data of an entry read from the cache memory by the storage content of the register and the offset unit of the logical address. 2. The comparison unit detects that the old cache read unit and the new cache read unit match each other, and obtains the tag address of the entry read from the cache memory and the address translation device. Data output means for outputting the read data of the entry read from the cache memory by the old cache read section stored in the register and the offset section of the logical address when the physical address upper section matches The information processing apparatus according to claim 1, further comprising: 3. When the comparison unit detects that the old cache read unit and the new cache read unit do not match, the state of the central processing unit is held for the next one cycle. 2. The information processing apparatus according to claim 1, further comprising holding requesting means for requesting the central processing unit. 4. A central processing unit for generating a logical address, a cache memory of a direct map system or a set associative system in which an entry consisting of a tag address and data is stored, and a higher part of the logical address is a physical address higher order. An address translation device for translating into parts,
The high-order part of the logical address, which is provided in correspondence with the value of the high-order part of the logical address and which is used in the reading of the cache memory of the address translation device and includes the corresponding cache read part, is input. A plurality of address conversion units that output a hit signal in the case of a cache memory, and the cache memory by the hit signal from any one of the plurality of address conversion units and an offset unit composed of a lower part of the logical address that is not address-converted. An information processing apparatus, characterized in that the entry stored in is read. 5. The first entry selection means for selecting a plurality of entries of the cache memory by the offset part of the logical address, and the first entry selection based on a hit signal from any of the address conversion parts. The information processing apparatus according to claim 4, further comprising a second entry selecting unit that selects one of the plurality of entries selected by the unit. 6. A central processing unit for generating a logical address, a cache memory of a direct map system or a set associative system in which an entry consisting of a tag address and data is stored, and an upper part of the logical address is set as a physical address upper part. An address translation device for translating into parts,
The read information of the entry provided in the address translation device and stored in the cache memory is stored, and when the entry corresponding to the higher physical address obtained by the address translation device is stored in the cache memory, A read information storage unit for outputting read information is provided, and an entry stored in the cache memory is read by the read information from the read information storage unit and an offset unit composed of a lower part of the logical address that is not subjected to address translation. An information processing apparatus having the above-mentioned configuration. 7. A first selection of a plurality of entries in the cache memory according to an offset part of the logical address.
Entry selection means and second entry selection means for selecting one of the plurality of entries selected by the first entry selection means based on the read information from the read information storage section. The information processing apparatus according to claim 6, further comprising: