JP2641319B2 - Address translation buffer clear method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for clearing an address translation buffer, and more particularly to an address translation buffer clear system for partially clearing an address translation buffer at high speed.

[Conventional technology]

Conventionally, in a computer using a virtual storage method, it is necessary to convert a logical address into a real address in order to access a memory. In order to perform this address translation at high speed, an address translation buffer is used. FIG. 2 shows the configuration of the address translation buffer.

One element constituting the address translation buffer is called an entry. The entry is determined by a specific bit of a logical address, and a valid bit 50 indicating the validity of registered contents (to clear the entry, this entry is used). The value is set to 0), a logical address section 51 and a real page address section 52. This address translation buffer is usually composed of a RAM, and can only refer to one entry in one search. Therefore, when the address translation buffer is partially cleared, a counter is provided, the address of the address translation buffer is changed by the counter, all entries are searched, and the address translation buffer is partially cleared.

[Problems to be solved by the invention]

In the above-described partial clearing method of the address translation buffer, only one entry can be searched in one cycle, and clearing must be performed by referring to all entries. Therefore, it takes time for the same number of cycles as the number of entries. There is a disadvantage that the address translation buffer cannot be used during the partial clearing process, and the processing capability is reduced.

[Means for solving the problem]

The present invention provides an address translation buffer clearing system for partially clearing an address translation buffer composed of a partial logical address portion composed of a logical page address portion and a corresponding real page address portion. A logical address register that holds a logical address composed of a logical page address composed of a second partial address partially including the first partial address and a third partial address and an offset address; and the address translation buffer A group of latches for storing a bit portion used for comparison with the first partial address, which is a copy of a part of the partial logical address portion of all entries, and which is stored in the latch group output and the logical address register The data of the first partial address in the logical page address thus obtained. A comparator, a valid flag register having the same number of bits as the number of entries of the address translation buffer and storing a valid flag indicating whether each entry of the address translation buffer is valid or invalid; A valid flag selection circuit for selecting the valid flag corresponding to the address indicated by the partial address; an output of the partial logical address section accessed by the address indicated by the third partial address; A comparison circuit that performs comparison with a partial address, and outputs a conversion valid signal when the comparison matches and the valid flag selected by the valid flag selection circuit indicates validity; The partial logical address into the buffer and the real page In response to the address registration request, the address indicated by the second partial address is written to the address indicated by the third partial address of the partial logical address portion, and the third portion of the real page address portion is written. At the same time as writing the real page address prepared by the system in advance to the address indicated by the address, the third part is indicated by the first partial address in the latches in the latch group corresponding to the address indicated by the address. Address conversion buffer registering means for writing valid information to a corresponding bit of the address indicated by the third partial address of the valid flag register, and receiving a request for converting the logical address into the real address from the system. hand,
When the output of the comparison circuit is the conversion valid signal, the offset address in the logical address register is added to the real page address read at the address indicated by the third partial address of the real page address section. Address conversion means for outputting an address as the real address; and partial clear control for receiving the partial match clear instruction from the system and invalidating the valid flag corresponding to the entry in the latch group whose comparison in the comparator matches. Means.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of an address conversion block showing one embodiment of the present invention.

1 is a logical address register having a logical page address and an offset, 2 is an address translation buffer, 2-1 is a partial logical address portion of the address translation buffer 2, 2-2.
Is the logical address part 2- in the address translation buffer 2.
1 is a real page address portion corresponding to 1, 4 is a latch for storing a copy of a bit used for the partial match clearing process of the partial logical address portion 2-1, and 5 is a partial match clear in the output of the latch 4 and the logical address register 1. A partial match clear comparator for comparing with the bit used in the partial match clear comparator 6; a partial clear control circuit for determining an entry to be invalidated in the address translation buffer 2 from the match output of the partial match clear comparator 5 when the partial match clear is instructed; Reference numeral 7 denotes a valid flag register having the same number of bits as the number of entries of the address translation buffer 2 and storing a valid flag indicating whether each entry of the address translation buffer is valid or invalid. 8 denotes a valid flag of the address translation buffer 2 accessed by a logical address. A valid flag selection circuit for selecting a valid flag corresponding to the entry; A comparison circuit 10 detects whether the output of the logical address unit 2-1 matches the output of the logical address register 1, and detects the validity of the entry. Reference numeral 10 denotes a partial logical address unit 2-1 and a real page address unit 2-2. Address translation buffer registering means for registering an address, 11 address translation means for translating a logical page address into a real page address,
Is an address signal used as a part of the logical address as an address of the address conversion buffer 2, 102 is an address signal used as a part of the logical address and used for partial match clear processing, 103 is a key part of the logical address and is an address conversion buffer. 2 is an address signal corresponding to the partial logical address section 2-1 and 104 is a partial match clear instruction signal indicating a partial match clear instruction.

When registering a partial logical address and a real page address in the address translation buffer 2, the contents of the logical address signal 103 are stored in the address indicated by the address signal 101 of the partial logical address section 2-1 by the address translation buffer registering means 10. Address signal 101 of real page address section 2-2
At the same time as writing the real page address prepared by the system in advance to the address indicated by, the contents of the address signal 102 and "1" are written to the latch 4 and the valid flag register 7 corresponding to the write entry of the address conversion buffer 2, respectively. .

If the address conversion buffer 2 has an access to convert a logical address to a real address, the read data of the partial logical address section 2-1 matches the contents of the address signal 103 in the comparison circuit 9 and the valid flag selection circuit 8 When the output is “1”, that is, when the output of the comparison circuit 9 indicates a hit, the address conversion means 11 uses the address of the address signal 101 of the logical address register 1 in the real page address section 2-2 of the address conversion buffer 2. The offset in the logical address register 1 is added to the real page address of the indicated entry and output as a real address (not shown). At this time, the latch 4, the partial match clear comparator 5, and the partial clear control circuit 6 are not used.

Next, when the partial match clear instruction signal 104 becomes “1”,
Partial clearing of the address translation buffer 2 is performed. Partial clearing of the address translation buffer 2 is to clear a bit of the valid flag register 7 corresponding to an entry in the latch group 4 of the latch having latch data matching the content indicated by the address signal 102 of the logical address register 1. . Therefore, first, the address signal 102, which is a partial signal of the logical address, is compared with the output of the latch 4 by the partial match clear comparator 5, and a comparison signal for all entries is sent to the partial clear control circuit 6. The partial clear control circuit 6 instructs the valid flag register 7 from the output of the partial match clear comparator 5 to reset the flag corresponding to the entry that matches the content of the address signal 102. The valid flag register 7 writes “0” to all valid flags corresponding to the entry specified by the partial clear control circuit 6. As a result, the partial clear of the valid flag specified by the partial match clear instruction, that is,
Partial clearing of the address translation buffer 2 is processed at one time.

〔The invention's effect〕

As described above, according to the present invention, the part to be compared by the partial match clear instruction of the logical address in the address translation buffer is duplicated, separately configured by a latch or the like, and designated by the partial match clear instruction via the comparator. Since the valid flag in the valid flag register corresponding to the entry of the latch having the latch data matching the content can be reset at a time, partial match clear of the address translation buffer can be performed at a time, and the processing capacity can be improved. It has the effect of improving.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an address translation buffer showing one embodiment of the present invention, and FIG. 2 is a configuration diagram of a conventional address translation buffer. 1 logical address register, 2 address conversion buffer, 2-1 partial logical address section, 2-2 actual page address section, 4 latch group, 5 partial match clear comparator, 6 ... partial clear control circuit, 7 ... valid flag register, 8 ... valid flag selection circuit, 9 ...
... Comparison circuit, 10 ... Address conversion buffer registration means, 11
…… Address conversion means, 50 …… Valid bit, 51 ……
Logical address part, 52... Real page address part.

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-138654 (JP, A) JP-A-50-40239 (JP, A) JP-A-64-28757 (JP, A)

Claims (1)

(57) [Claims] In an address translation buffer clearing system for partially clearing an address translation buffer composed of a partial logical address portion composed of a logical page address portion and a corresponding real page address portion, a first partial address is used. A logical address register for holding a logical address composed of a logical page address composed of a second partial address partially including the first partial address and a third partial address and an offset address, and the address conversion buffer A group of latches for storing a bit portion used for comparison with the first partial address, which is a copy of a part of the partial logical address portion of all entries, and which is stored in the latch group output and the logical address register With the data of the first partial address in the logical page address A valid flag register having the same number of bits as the number of entries in the address translation buffer and storing a valid flag indicating whether each entry in the address translation buffer is valid or invalid. A valid flag selection circuit that selects the valid flag corresponding to the address indicated by the partial address; an output of the partial logical address unit accessed by the address indicated by the third partial address; And a comparison circuit that outputs a conversion valid signal when the comparisons match and the valid flag selected by the valid flag selection circuit indicates validity. The partial logical address and the real In response to the registration request of the page address, the address indicated by the second partial address is written to the address indicated by the third partial address of the partial logical address section, and the third page of the real page address section is written. At the same time as writing the real page address prepared by the system in advance to the address indicated by the partial address, the real page address is indicated by the first partial address in the latches in the latch group corresponding to the address indicated by the third partial address. Address conversion buffer registering means for writing valid information to a corresponding bit of the address indicated by the third partial address of the valid flag register, and receiving a request for converting the logical address into the real address from the system. When the output of the comparison circuit is the conversion valid signal, Address conversion means for outputting, as the real address, an address obtained by adding the offset address in the logical address register to the real page address read at the address indicated by the third partial address of the page address section; An address translation buffer clear method, comprising: a partial clear control unit for receiving a partial match clear instruction and invalidating the valid flag corresponding to the entry in the latch group whose comparison in the comparator matches.