JPS6366430B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a highly efficient semiconductor device that can perform ultra-high-speed, high-power operation.

[Conventional technology]

In conventional semiconductor devices, since the main current passes through the base, which is the control electrode, it is not possible to increase the impurity density of the base beyond a certain level, and the lateral resistance of the base increases, causing the base resistance R and its capacitance C to increase.
Since the R·C time constant determined by becomes large, the upper limit of usable frequency is limited. In other words, in conventional transistors, when the element transitions from a blocking state to a conducting state (hereinafter this state is referred to as turn-on), the on-state region is The spread cannot be controlled quickly and the turn-off time cannot be shortened.
Furthermore, when transitioning from a conducting state to a blocking state (hereinafter this state is referred to as turn-off), a large number of majority carriers and minority carriers injected into the junction in the on state move by diffusion. However, since it is absorbed by the electrode and disappears, it takes a long time. Furthermore, since the lateral resistance of the base is large, the voltage applied to the base via the base electrode terminal to turn it off does not strongly affect the far region away from the base terminal, and the voltage applied to the base electrode is slightly Simply turning off the vicinity increases the turn-off time during which the carrier is ejected from the entire base region.

Furthermore, in transistors as well, as the lateral resistance of the base increases, the effect of the voltage applied to the base electrode is not strong enough to reach parts of the base region away from the base electrode, which limits the usable frequency.

[Problem to be solved by the invention]

That is, conventional semiconductor devices have the problem of being incapable of ultra-high-speed, high-power operation and of poor efficiency.

On the other hand, in a thyristor, in order to substantially reduce the base lateral resistance, a high impurity density region of the same conductivity type as the base region is provided in contact with the side of the base region that is connected to the cathode, and a large number of small holes are formed in the region. The structure is the same as the structure in which the base region runs through and is in contact with the cathode region (Japanese Patent Publication No. 44-30535), or the base region in which many small holes are similarly drilled in the base region away from the joints on both sides of the base region. A structure in which a conductive type high impurity density layer is formed has been proposed (Japanese Patent Laid-Open No. 77585/1985), but in the former, this high impurity density region is bonded to a relatively high density layer on the cathode side. Therefore, the depletion layer does not extend much, the distributed capacitance is large, and the switching time becomes long. Furthermore, in the latter case, since the high impurity density region is located in the middle of the base, in addition to the above-mentioned drawback, the number of manufacturing steps is increased.

In addition, transistors have a structure in which a high impurity density region of the same conductivity type as the base region is buried in the base region away from the junctions on both sides of the base region (Japanese Patent Application Laid-Open No. 50-26480, 5273), and a structure in which a high impurity density region of the same conductivity type as the base region is buried in the base region and collector region around the base-collector junction (Japanese Patent Application Laid-Open No.
22885), but the former has the drawbacks that the depletion layer does not extend due to this high impurity density region and the switching time becomes long, and the manufacturing process is increased, and the latter has the disadvantage that the base collector Disadvantages include an increase in the distributed capacitance of the junction, which increases the switching time, and a decrease in the base-collector breakdown voltage, resulting in a decrease in the handling power.

This invention was made to eliminate the above-mentioned drawbacks of the conventional devices, and its purpose is to provide a novel transistor semiconductor device that can operate at ultra-high speed and with high power, has high efficiency, and can also be applied to DC interruption. There is a particular thing.

[Means to solve the problem]

The semiconductor device according to the present invention has approximately 1×
a first semiconductor layer consisting of a low impurity density region having an impurity density of 10 ¹¹ cm ^-3 to 10 ¹⁶ cm ^-3 ; a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer; In a transistor formed of a semiconductor layer and a third semiconductor layer of the same conductivity type, the first semiconductor layer is arranged in the second semiconductor layer on the same plane as the first semiconductor layer of low impurity density. Approximately 1× of the same conductivity type as the second semiconductor layer, in contact with the layer only
High impurity density semiconductor regions having an impurity density of 10 ¹⁷ cm ^-3 or more are formed in substantially parallel lines, and the high impurity density semiconductor regions in the second semiconductor layer are used as base electrodes.

[Effect]

In this invention, the lateral resistance of the second semiconductor layer (base) is reduced by the high impurity density semiconductor regions formed in substantially parallel lines, and the distributed capacitance between the second semiconductor layer (base) and the first semiconductor layer (collector) is reduced. decreases.

〔Example〕

Hereinafter, the transistor of the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an example of an npn type transistor of the present invention.

n-type first layer 6, p-type second layer 7, n-type third layer
It has a three-layer structure with layer 8, and the second layer is the base.
The layer 7 has a p ⁺ region 9 with a relatively high impurity density, which is arranged on the same plane as the p region with ^a relatively low impurity density and is in contact with the third layer 8.
are almost all connected to each other. The effect of the p ⁺ region 9 is that the lateral resistance of the base is reduced, so that the effect of the voltage applied to the base quickly extends to the region far from the base terminal, and
By expanding the depletion layer in the layer 8, the distributed capacitance is reduced, and the flow rate of the carrier can be easily controlled. In the case of transistors, there are also pnp type, pnip type, npin
Of course, the same applies to types.

As explained above, this invention is a transistor in which carriers can be sufficiently controlled by easily expanding the depletion layer from the P ⁺ layer in the base to the n ^- layer or n ⁺ layer. The total area of the ⁺ region should be, for example, less than half of the total area of the junction so that it does not interfere with the main current passing through the base, and in order to lower the base resistance,
It is characterized by the shape of the p ⁺ layer.

It is more effective to reduce the base resistance if the p ⁺ regions of the base are arranged in substantially parallel lines.

FIG. 2 shows a p ⁺ region 9 only in the second layer 7 of FIG.
FIG. 3 is a perspective view of a case where the wafers are arranged in substantially parallel lines, as seen from the bottom side of the figure. p ⁺ region 9 in p region 2
It can be seen that the beams are arranged in substantially parallel lines at predetermined intervals (hereinafter, this will be referred to as a beam type, and the base having the beam type will be referred to as a beam base). When the p ⁺ regions are arranged in a beam shape in this way, the ratio of the p ⁺ regions to the total junction area becomes the smallest. That is, the degree of interference with the main current is minimal, and the distributed capacitance and base resistance can be made very small. By reducing the CR time constant of the base, the operating speed becomes very fast. Since the p ⁺ region 9 in the base faces the main current path and current flows uniformly, it is possible to easily increase the area, that is, increase the power.

FIG. 3 shows an example of a beam-based application, showing the second layer 7 from the same position as in FIG. The beam-shaped p ⁺ regions 9 are connected to each other by linear p ⁺ regions 11, and the spacing between the two is ten times or more the spacing between the former beam-like p ⁺ regions 9. By doing so, each base resistance is reduced to about 1/10 or less. This shape of the base reduces the lateral resistance of the base in all directions. Even though the base resistance has become extremely small, it has the advantage that even if the beam-shaped p ⁺ region 9 is interrupted in the middle during manufacturing, the p ⁺ region connection can be maintained over the entire surface. It is suitable for passing large currents compared to the semiconductor device shown. In addition, in the case of structures with opposite conductivity types, p ⁺ ,
Of course, the p region becomes an n ⁺ , n region.

In the transistor of this invention, by forming the p ⁺ layer in the base as shown in Figure 3, the base resistance can be made extremely small, resulting in improved switching characteristics and stability when temperature rises. This will make a major contribution. The transistor of this invention has an extremely good injection efficiency from the emitter to the base because the main current path is divided into the base layer and the p ⁺ layer in a beam shape, and the base resistance is small and the switching speed is fast. It will have the following characteristics.

The structure of the semiconductor device of the present invention can also be used as a radiation sensor semiconductor device, such as a photothyristor or a phototransistor, since carriers generated by incident light move quickly by passing through the high impurity density region of the base. Speeding up,
A large area can be achieved. Of course, this applies not only to light but also to radiation in general.

Next, a method for manufacturing the semiconductor device of the present invention shown in FIG. 1 will be described below. FIGS. 4a to 4h are process diagrams showing an example of the manufacturing process in cross section.

A silicon n ^- type substrate 3 with a specific resistance of about 1KΩ-cm
(a) Etched to about 100 μm and strain-corrected p ⁺ region 5 on one side (impurity density about 1 × 10 ²¹ cm ^-3 )
is epitaxially grown to about 2 μm at 1050℃ (b), p ⁺
Area 5 is left in the form of a beam with a width of 5 μm and an interval of 15 μm, and the unnecessary portion is etched by 2.5 μm (c). P ^layer 2 (1×10 ¹⁶
cm ^-3 degree) was epitaxially grown to 5 μm at 1050°C.
(d), and further on top of that is a strain-corrected n ⁺ layer 1 (1×10 ²¹
cm ^-3 ) to 1 μm epitaxial growth (e).

A part of the beam-shaped p ⁺ region 5 is exposed by etching a part in a stepwise manner from either side.
(f), After etching the back surface of the substrate 3 by 10 μm, a strain-corrected n ⁺ layer 4 is diffused over the entire surface at 1000°C on the back surface of the substrate (g), and finally, metal 1 is formed as each electrode terminal.
Add 2 to complete (h). The silicon n ^- type substrate 3 is
In order to increase the collector voltage resistance, for example, 300~
It is preferable to set it to 500μm. Of course, if the thickness is increased in this way, the resistance during conduction will be extremely increased.
Here, the beam-shaped p ⁺ region 5 is formed not by epitaxial growth but by a selective diffusion method in which impurities are added at 1100°C for 10 minutes and then heat-treated in oxygen at 1200°C for 5 minutes, and the ion implantation amount is 1. ×10 ¹⁵ cm ^-2 , acceleration voltage
After selective ion implantation at 300KeV, 30 at 1100℃
Various methods such as heat treatment can be used, and the same applies to the formation of other regions. To take out the base terminal, a high impurity density region of the same conductivity type as the base region may be formed from the surface by deep diffusion. Furthermore, the order in which the regions are formed may also be different from this example.

Although the structural example has been shown above, the present invention is not limited to this, and it goes without saying that structures of opposite conductivity type may be used.

All numerical values such as impurity density, thickness, temperature, time, etc. mentioned in the production examples are not limited to the examples listed here, but can be realized by changing them in various ways depending on the design conditions, and distortion correction may also be applied depending on the case. is not necessary.
The impurity density of the high impurity density region, that is, the p ⁺ region 5 is, for example, 10 ¹⁷ cm ^-3 to 10 ²¹ cm ^-3 , and the impurity density of the low impurity density region, that is, the n ^- type substrate 3 is, for example, 10 ¹¹ cm ^-3 to 10 ¹⁶ cm ^-3 .

Furthermore, the material is not limited to silicon, but may also be germanium, or compound semiconductors such as gallium arsenide, gallium aluminum arsenic, indium arsenic phosphorus, etc.Also, although epitaxial growth has been explained as an example, It may also be manufactured by forming a heterojunction.

〔Effect of the invention〕

As explained above, the semiconductor device of the present invention has a lower lateral resistance of the base than a normal transistor, and a better distribution of the base region than the conventional one in which a high impurity density region is formed in the base. Since the capacity is smaller, the speed can be increased compared to the conventional one, and it is easier to increase the area for higher power. Furthermore, the base input signal of a transistor with this structure can be changed in various ways depending on the design. That is, by changing the thickness of the relatively low impurity density region of the base region, the state of the depletion layer formed in the region adjacent to the high impurity density region of the base can be changed. For example, it turns on even when the base input is 0,
Off You can set various states.

As described above, the semiconductor device of the present invention has extremely high industrial value.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing one embodiment of the transistor of the present invention, FIGS. 2 and 3 are perspective views of only the second layer viewed from below in order to show an example of the shape of the base in FIG. FIG. 4 is a cross-sectional view showing the manufacturing process of the transistor shown in FIG. 1. In the figure, 2 is the p-type second layer/base, 6 is the n-type
type first layer, 7 is a p-type second layer/base, 8 is an n ^- type third layer, 9 is a p ⁺ region in the base, 10 is a beam-shaped p ⁺ region, 11 is a beam-shaped p ⁺ region mutually is a p ⁺ region that connects to. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first semiconductor layer made of a low impurity density having an impurity density of approximately 1×10 ¹¹ cm ^-3 to 10 ¹⁶ cm ^-3 , and a first semiconductor layer of a conductivity type opposite to that of the first semiconductor layer. a second semiconductor layer, and a third semiconductor layer of the same conductivity type as the first semiconductor layer.
In the transistor formed of a semiconductor layer, the second semiconductor layer is arranged in the second semiconductor layer on the same plane as the first semiconductor layer having a low impurity density and is in contact only with the first semiconductor layer. High impurity density semiconductor regions having an impurity density of approximately 1×10 ¹⁷ cm ^-3 or more and having the same conductivity type as the semiconductor layer in the second semiconductor layer are formed in substantially parallel lines, and the high impurity density semiconductor region in the second semiconductor layer A semiconductor device characterized in that a region is used as a base electrode. 2. The high impurity density regions in the second semiconductor layer are formed by connecting high impurity density semiconductor regions formed on substantially parallel lines to each other, and the spacing between the regions is at least 10 times the spacing between the parallel linear regions. A semiconductor device according to claim 1, characterized in that: