JPS6364399A - Ceramic multilayer board - Google Patents

Ceramic multilayer board

Info

Publication number
JPS6364399A
JPS6364399A JP20828586A JP20828586A JPS6364399A JP S6364399 A JPS6364399 A JP S6364399A JP 20828586 A JP20828586 A JP 20828586A JP 20828586 A JP20828586 A JP 20828586A JP S6364399 A JPS6364399 A JP S6364399A
Authority
JP
Japan
Prior art keywords
conductor
ceramic
insulator
glass
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20828586A
Other languages
Japanese (ja)
Other versions
JPH0797703B2 (en
Inventor
島崎 新二
浩一 熊谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61208285A priority Critical patent/JPH0797703B2/en
Publication of JPS6364399A publication Critical patent/JPS6364399A/en
Publication of JPH0797703B2 publication Critical patent/JPH0797703B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、セラミック多層基板、特に低温焼成可能なセ
ラミック多層基板に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a ceramic multilayer substrate, particularly a ceramic multilayer substrate that can be fired at a low temperature.

従来の技術 近年、電子回路には、厚膜印刷法により簡単に回路形成
できる熱放散性の優れたセラミック基板を使用した電子
回路が使用されている。そして、より小型高性能化を実
現する為に多層電子回路基板が使用され始めている。
BACKGROUND OF THE INVENTION In recent years, electronic circuits using ceramic substrates with excellent heat dissipation properties, which can be easily formed by thick film printing, have been used in electronic circuits. Multilayer electronic circuit boards are beginning to be used to achieve smaller size and higher performance.

多層回路基板を製造する方法は一般的には次に述べる(
a) 、 (b) 、 (C)の三種類がある。
The method for manufacturing multilayer circuit boards is generally described below (
There are three types: a), (b), and (C).

(a)  セラミック焼結体上での印刷多層法(b)グ
リーンシート上での印刷多層法(C)  グリーンシー
ト積層多層法 (a)のセラミック焼結体上での印刷多層法をでよる多
層基板の製造方法全説明すると、第1図にそのプロセス
を示すように、まず基板となるセラミック焼結体上に第
1導体層を印刷・乾燥・焼成しくステップ1〜3)、次
に第1絶縁層全印刷・乾燥・焼成しくステップ4〜6)
、その上K M 2 M縁層を印刷・乾燥しくステップ
7.8)、第2導体層を印刷・乾燥しくステップ9,1
0)、第2絶縁層ごと一括焼成(ステップ11)する。
(a) Multi-layer printing method on ceramic sintered body (b) Multi-layer printing method on green sheet (C) Multi-layer printing method on green sheet lamination multi-layer method (a) Multi-layer printing method on ceramic sintered body To explain the entire manufacturing method of the board, as shown in Fig. 1, first the first conductor layer is printed, dried, and fired on the ceramic sintered body that will become the board (steps 1 to 3), and then the first Complete insulating layer printing, drying, and baking Steps 4 to 6)
, then print and dry a K M 2 M edge layer (step 7.8), print and dry a second conductor layer (step 9, 1).
0), the second insulating layer is fired all at once (step 11).

この際、第1及び第2絶蘇層はグイアホールと呼ばれる
微小孔が形成されるように印刷し、その微小孔中に第2
導体層に用いられる材料が充填されるように第2導体層
を印刷する事により@11導層と第2導体層とが接続さ
れる。次に第2導体層上に第3絶縁層を印刷・乾燥・焼
成し、第2絶縁層以降と同手順で層数を重ねていく(ス
テップ1〜11)。
At this time, the first and second resuscitation layers are printed so that micropores called guiaholes are formed, and the second
The @11 conductive layer and the second conductive layer are connected by printing the second conductive layer so that it is filled with the material used for the conductive layer. Next, a third insulating layer is printed, dried, and fired on the second conductor layer, and the layers are stacked in the same manner as after the second insulating layer (steps 1 to 11).

(b)のグリーンシート上での印刷多層法による多層基
板の製造方法は、第2図にそのプロセスを示すように、
まず焼成後基板となるセラミックのグリーンシート上に
第1導体層を印刷・乾燥しくステップ12.13)、次
にその上に第1絶縁層を印刷・乾燥しくステップ14.
15)、引き続き第2導体層、第2絶縁層の印刷・乾燥
全行ない(ステップ16〜19)、以降同手順で層数を
繰り返しくステップ12〜19)、グリーンシートと導
体層と絶縁層と?−一括焼成る(ステップ20)。
The method for manufacturing a multilayer board using the printing multilayer method on a green sheet (b) is as shown in Figure 2.
First, print and dry the first conductor layer on the ceramic green sheet that will become the substrate after firing (step 12.13), then print and dry the first insulating layer thereon (step 14).
15), Continue printing and drying the second conductive layer and second insulating layer (steps 16 to 19), repeat the same procedure for each layer from then on (steps 12 to 19), and print the green sheet, conductor layer, and insulating layer. ? - Batch firing (step 20).

(C)のグリーンシート積層多層法による多層基板の製
造方法は、第3図にそのプロセスを示すように、まず複
数枚のセラミックのグリーンシートそれぞれに異なるパ
ターンの微小孔を形成しくステップ22〜24)、それ
ぞれ異なるパターンの導体層を印刷−乾燥する(ステッ
プ26〜30)。次に導体パターンの異なるグリーンシ
ート同士を所望枚数積層しくステップ31)、適度な圧
力と適度な温度のもとで圧着しくステップ32)、所望
の外形寸法に切断してから焼成する(ステップ33゜3
4)。各導体層間の導通はグリーンシートの微小孔に充
填された導体によシ行なわれる。
As shown in FIG. 3, the method for producing a multilayer board using the green sheet lamination multilayer method (C) first involves forming micropores with different patterns in each of a plurality of ceramic green sheets in steps 22 to 24. ), printing and drying conductor layers with different patterns (steps 26 to 30). Next, a desired number of green sheets with different conductor patterns are stacked together (step 31), crimped together under appropriate pressure and temperature (step 32), cut into desired external dimensions, and fired (step 33). 3
4). Electrical conduction between each conductor layer is achieved by conductors filled in micropores in the green sheet.

伽) 、 (C)の製造方法においては共に基板焼成の
後に最上層の厚膜形成を行なう(ステップ21.35)
In both the manufacturing methods of (B) and (C), the thick film of the top layer is formed after baking the substrate (step 21.35).
.

(a)、申) 、 (C)三種類の製造方法を比奴する
と、(、)は比較的簡単な技術で多層化が可能であるが
、実質的な層数限界は4〜6層でありそれ以上の暦数は
表面の凹凸が激しくなり実用に討えない。■)はグリー
ンシートと印刷した絶縁層と導体層とk 一度に焼成す
る事によりプロセスの合理化を行なう事ができる。しか
しくb)も(a)同様に、層数全増すと表面の凹凸が大
きくなるのでやはり限界層数は4〜6層である。(C)
は理論的に層数は無限に可能であり、現実的にも3o〜
40層程度の多層基板が報告されている。しかし、その
製造にはきわめて高度な技術を要し、プロセス及び材料
的な課題も多い。
Comparing the three types of manufacturing methods (a), (mon), and (c), (,) can be multi-layered with relatively simple technology, but the practical limit on the number of layers is 4 to 6 layers. If the number of calendars is larger than that, the surface becomes too uneven to be used in practical use. ■) The process can be streamlined by firing the green sheet, printed insulating layer, and conductive layer at the same time. However, in case of b), similarly to (a), if the total number of layers is increased, the surface unevenness becomes larger, so the limit number of layers is still 4 to 6 layers. (C)
The number of layers is theoretically possible to be infinite, and realistically it is 3o ~
A multilayer substrate with about 40 layers has been reported. However, their production requires extremely advanced technology, and there are many process and material issues.

以上(a) 、 (b) 、 (C)三種類の製造方法
のうち、本発明は(C)のグリーンシート積層多層法に
関するものである。この(C)のタイプの基板に使用さ
れるセラミック絶縁体はAl2O3を主成分とするため
焼結温度が1500〜1600℃と極めて高いので、回
路を4成する導体材料もかかる焼結温度で劣化しないW
、Mo等の金属を使用せざるをえない。これらW、Mo
は酸化されやすいため還元雰囲気で焼成する必要がある
ので作業性が劣った。近年、上記のような作業性の問題
を解決した新しい低温焼結タイプのセラミック多層基板
の提案がなされている(特願昭60−103075号、
特願昭60−236744号、特願昭58−17651
号、特題昭58−108792号、特願昭58−176
9541セラミック絶縁体にガラスとアルミナとの混合
物を用い焼結温度を1000℃以下と低温化させ、その
結果、内部導体にA9/Pd系の非酸化性低融点金属を
用いることが可能となり還元雰囲気での焼成は不必要と
なった。
Among the above three manufacturing methods (a), (b), and (C), the present invention relates to (C) the green sheet lamination multilayer method. Since the ceramic insulator used for this type (C) board is mainly composed of Al2O3, the sintering temperature is extremely high at 1,500 to 1,600°C, so the conductor material that makes up the circuit also deteriorates at such a sintering temperature. No W
, Mo, and other metals must be used. These W, Mo
Because it is easily oxidized, it must be fired in a reducing atmosphere, resulting in poor workability. In recent years, proposals have been made for new low-temperature sintering type ceramic multilayer substrates that solve the workability problems described above (Japanese Patent Application No. 103075/1983).
Patent Application No. 1982-236744, Patent Application No. 58-17651
No., special title No. 1987-108792, patent application No. 1987-176
A mixture of glass and alumina is used for the 9541 ceramic insulator, and the sintering temperature is lowered to below 1000°C.As a result, it is possible to use A9/Pd-based non-oxidizing low melting point metals for the internal conductor, which allows for a reducing atmosphere. Firing is no longer necessary.

発明が解決しようとする問題点 しかしながら、上記のような従来技術を用いて。The problem that the invention seeks to solve However, using the prior art techniques as mentioned above.

単純に絶縁材料をガラスとアルミナとの混合物、つフリ
ガラスセラミックスとし、一方向部導体をAg、Pdの
単体あるいはこれらの合金、混合体とするのみでは第3
図に従いセラミック多層基板を作成しても、第4 四k
) +に)に示すように焼成後、導体36の内蔵してい
る部分と、内蔵していない問題がある。又前記既出頭に
は、単にガラスセラミックスの焼結温度が1000℃以
下となることを特徴とするものや、ガラスセラミックス
の軟化温度Tsが400℃≦Ts≦750℃であること
を特徴とするもので、内部導体との組み合わせにおいて
制御されるべき必要な内容については提案されていなか
った。
If the insulating material is simply a mixture of glass and alumina, or glass ceramics, and the one-way conductor is Ag or Pd alone, or an alloy or mixture thereof, the third
Even if you create a ceramic multilayer board according to the diagram, the 4th 4k
) As shown in +), after firing, there are some parts where the conductor 36 is built-in and some parts where it is not built-in. In addition, the above-mentioned publications include those characterized simply in that the sintering temperature of the glass ceramics is 1000°C or less, and those characterized in that the softening temperature Ts of the glass ceramics is 400°C≦Ts≦750°C. However, the necessary contents to be controlled in combination with the internal conductor were not proposed.

本発明は上記の問題点に鑑み、絶縁材料にガラスとアル
ミナとの混合物であるガラスセラミックスを使用し、導
体材料にはA、g、Pdの単体あるいはこれらの合金、
混合体である非酸化性低融点金属を使用し、上記組み合
わせで焼成時基板変形がない空気中低温焼成可能なセラ
ミック多層基板を提供するものである。
In view of the above problems, the present invention uses glass ceramics, which is a mixture of glass and alumina, as an insulating material, and as a conductive material, A, g, Pd alone or an alloy thereof,
The present invention uses a mixture of non-oxidizing low melting point metals and uses the above combination to provide a ceramic multilayer substrate that can be fired in air at low temperatures without causing substrate deformation during firing.

問題点を解決するための手段 上記問題点を解決するために本発明の第1の発明におけ
るセラミック多層基板は、絶縁体に用いるガラスセラミ
ックスのガラス軟化点Tsと内部導体Ag/Pd (組
成二(100−x ’)Ag−x Pd 。
Means for Solving the Problems In order to solve the above problems, the ceramic multilayer substrate according to the first aspect of the present invention has a glass softening point Ts of the glass ceramic used for the insulator and an internal conductor Ag/Pd (composition 2 ( 100-x')Ag-xPd.

Qwt%≦x≦sowt%)との間でTS≦ Cx+3
0)、+464じC〕 の関係式が成シ立つことを特徴
とするものである。又第2の発明におけるセラミック多
層基板は、導体としてガラス軟化点が基板絶縁体のそれ
と同等かあるいはそれ以上である無機材料を5〜10重
量ヂ含有するものでちる。更に第3の発明におけるセラ
ミック多層基板は、導体に含有する導電性金属粉の含有
量が55〜7Q重量裂とするものである。
Qwt%≦x≦sowt%), TS≦Cx+3
0), +464jiC]. The ceramic multilayer substrate according to the second aspect of the present invention contains 5 to 10 weight parts of an inorganic material having a glass softening point equal to or higher than that of the substrate insulator as a conductor. Further, in the ceramic multilayer substrate according to the third invention, the content of conductive metal powder contained in the conductor is 55 to 7Q by weight.

作  用 本発明のセラミック多層基板は1000℃以下で焼成可
能なガラスとアルミナとの混合物であるガラスセラミッ
クスとAg、Pdの単体あるいは合金。
Function The ceramic multilayer substrate of the present invention is made of a single substance or an alloy of glass ceramics, which is a mixture of glass and alumina, which can be fired at 1000° C. or lower, and Ag and Pd.

混合物からなる導体とから構成されておシ空気中低温焼
成可能である。
It is composed of a conductor made of a mixture and can be fired at a low temperature in air.

さらに本発明のセラミック多層基板は特に焼成時に導体
が内蔵している部分とそうでない部分との間での寸法変
化量の差がなく基板の変化が全く発生しない。
Furthermore, in the ceramic multilayer substrate of the present invention, there is no difference in the amount of dimensional change between the portion where the conductor is built in and the portion where the conductor is not, especially during firing, and no change in the substrate occurs at all.

本発明の限定理由は次の通りである。The reasons for the limitations of the present invention are as follows.

多層基板の焼成時における収縮曲線を第6図。FIG. 6 shows the shrinkage curve during firing of the multilayer substrate.

第6図、第7図に示す。まず第5図のように導体の収縮
開始点が絶縁体よりも低温度の場合、温度T1にて絶縁
体はPa1nt aの如く多少収縮を開始している。こ
の時点で絶縁材料は軟化の状態にある。一方T1での導
体はPo1nt  bの如くすでにより大きく収縮が進
行しており周囲の絶縁体はこの導体の大きな変化に引き
づられ収縮をしてゆく、さらに温度が上昇しT2となっ
た場合、Pa1nt cの如く導体はすでに収縮を完了
している。他方絶縁体はPo1nt dにて変わらずに
収縮が進行している。温度T2における絶縁体の動きに
対して導体はすてに収縮を完了しているので導体の内蔵
している基板部分の寸法変化は生じない。しかし導体の
内蔵していない基板部分は、温度T3の絶縁体の収縮完
了Pa1nt e  まで収縮を続行し、その結果第4
図(b)の焼成後に示すような導体内蔵部が非内蔵部に
比べて大きくなるような基板変形が生じるのである。
It is shown in FIGS. 6 and 7. First, as shown in FIG. 5, when the contraction start point of the conductor is at a lower temperature than that of the insulator, the insulator begins to contract to some extent at temperature T1 as shown in Pa1nt a. At this point the insulating material is in a softened state. On the other hand, the conductor at T1, like Po1nt b, is already shrinking more greatly, and the surrounding insulator is dragged by the large change in the conductor and shrinks.If the temperature rises further and reaches T2, The conductor has already completed its contraction as in Palnt c. On the other hand, the shrinkage of the insulator continues unchanged at Po1nt d. Since the conductor has already completely contracted in response to the movement of the insulator at the temperature T2, no dimensional change occurs in the part of the substrate in which the conductor is built. However, the part of the board that does not have a built-in conductor continues to shrink until the insulator completes shrinking at temperature T3, and as a result, the fourth
After firing in Figure (b), the substrate is deformed such that the conductor built-in portion becomes larger than the non-conductor built-in portion.

他方、第6図のように絶縁体の収縮開始点が導体よりも
低温度の場合、温度T1にて導体はPo1ntfのごと
く多少収縮を開始している。この時点で導体は軟化の状
態である。一方T1 での絶縁体はPa1nt gの如
くすでに大きく収縮が進行してお多導体はこの絶縁体の
大きな変化に引きづられ収縮してゆく。基板を構成する
絶縁体は導体に比べ量が非常に多いため温度T1 での
基板の収縮は導体が内蔵されているか否かにかかわらず
全体として均一に進行して行く。さらに温度が上昇しT
2となった場合、Pa1nt i の如く絶縁体は、す
でに収縮を完了し固化しているためPo1nt h の
ような導体の変化に対して基板全体としては収縮は発生
しない。従って第4スル)に示すような焼成時の基板変
形は発生しない。
On the other hand, when the contraction start point of the insulator is at a lower temperature than that of the conductor as shown in FIG. 6, the conductor begins to contract somewhat at temperature T1 as shown in Po1ntf. At this point, the conductor is in a softened state. On the other hand, the insulator at T1 has already undergone significant contraction as shown in Pa1ntg, and the multiconductor is dragged along by this large change in the insulator and contracts. Since the amount of the insulator constituting the substrate is much larger than that of the conductor, the shrinkage of the substrate at temperature T1 progresses uniformly as a whole regardless of whether a conductor is built-in or not. The temperature further rises
2, the insulator, such as Pa1nt i , has already finished shrinking and solidified, so that the substrate as a whole does not shrink in response to a change in the conductor, such as Po1nt h . Therefore, the substrate deformation during firing as shown in the fourth case) does not occur.

さらに第7図のように導体と絶縁体の収縮開始点が一致
する場合、岡者の収縮変化が同一のため基板変形は発生
しない。
Further, when the contraction start points of the conductor and the insulator coincide as shown in FIG. 7, the change in contraction of the conductor is the same, so no substrate deformation occurs.

以上の第6図、第6ス、第7図にて説明した導体の収縮
開始点は導体材料がAglPd系の場合、Ag、Pdの
含有率によって太きぐ変化する。Pd比0〜30wt%
におけるAg/Pdペーストの収縮開始点の関係を第8
図に示す。Ag/PdペーストのPd含有率をxwt%
どした時のAg/Pdペースト(100−x )Ag 
−x Pdの収縮開始点は、第8図よシ次式■ H(X+30 ) + 464  [℃〕  ・・・・
・・・・・・・・・・・■で算出されることが明らかと
なった。さらに絶縁体の収縮開始点は絶縁材料を構成す
る無機粉体間の原子、イオンレベルの物質の拡散、再配
列が生ずる温度を意味するものでありマクロ的には、そ
の材料のガラス軟化点TS と一致する。従って上記基
板変形が発生しない条件は絶縁体のガラス軟化点Tsが
0式で示される導体の収縮開始点よシも同一か又は低温
であることが必要である。
When the conductor material is AglPd-based, the shrinkage start point of the conductor explained in FIGS. 6, 6, and 7 changes depending on the content of Ag and Pd. Pd ratio 0-30wt%
The relationship between the shrinkage start point of Ag/Pd paste in
As shown in the figure. Pd content of Ag/Pd paste is xwt%
Ag/Pd paste (100-x) Ag
-x The contraction start point of Pd is determined by the following formula in Figure 8: H(X+30) + 464 [℃]...
It has become clear that it is calculated by ・・・・・・・・・・・・■. Furthermore, the shrinkage start point of an insulator refers to the temperature at which diffusion and rearrangement of substances at the atomic and ion level between the inorganic powders constituting the insulating material occur, and from a macroscopic perspective, it is the glass softening point TS of the material. matches. Therefore, the condition under which the above-mentioned substrate deformation does not occur is that the glass softening point Ts of the insulator is the same as the shrinkage start point of the conductor, which is expressed by the equation 0, or is at a lower temperature.

Ts≦−(X+30 ) 2+464  口c〕・・・
・・川・■次に内部導体に絶縁体の軟化点Tsと同一か
それ以上の軟化点を持つ無機材料を含有させることによ
り導体の収縮開始点を絶縁材料のTsよりも高温ヘシフ
トさせ焼成時の変形を防ぐことができる。但し上記無機
材料の含有量が導体中5重量%未満の場合効果はない。
Ts≦-(X+30) 2+464 mouth c]...
... River ■Next, by incorporating an inorganic material with a softening point equal to or higher than the softening point Ts of the insulator into the internal conductor, the contraction start point of the conductor is shifted to a higher temperature than the Ts of the insulating material during firing. deformation can be prevented. However, if the content of the above-mentioned inorganic material is less than 5% by weight in the conductor, there is no effect.

一方10重量係を越える量を含有する場合は電気抵抗が
上昇し導体としての機能が劣ってしまう。
On the other hand, if the amount exceeds 10% by weight, the electrical resistance will increase and the function as a conductor will deteriorate.

さらに内部導体に含有する導電性金属の含有率は56〜
70重量係である必要がある。含有率が7o重量%を越
える場合、グリーンシート上に印刷形成された導体層中
の導電性金属粉は互いに非常に近接しており導体粉同士
の接触点が多い状態である。このような状態で焼成時の
工洋ルギーが加えられた場合、粉体間の原子及びイオン
の拡散が通常よりも容易に発生し、その結果、焼成収縮
開始点が絶縁材料のガラス軟化点Ts、!:!Slも低
温ヘシフトし、焼成時の基板変形が生ずる。導電性金属
が55重量%未満の場合、電気抵抗が上昇し、導体とし
ての機能が劣ってしまう。
Furthermore, the content of conductive metal in the internal conductor is 56~
Must be 70 weight class. When the content exceeds 70% by weight, the conductive metal powders in the conductor layer printed on the green sheet are very close to each other and there are many contact points between the conductor powders. If engineering energy is applied during firing in such a state, atoms and ions between the powders will diffuse more easily than usual, and as a result, the starting point of firing shrinkage will be the glass softening point Ts of the insulating material. ,! :! Sl also shifts to lower temperatures, causing substrate deformation during firing. If the content of the conductive metal is less than 55% by weight, the electrical resistance will increase and the conductor function will be poor.

実施例 (実施例1) 粒径0.5〜5 μmとしたB2O3−8iO2系ガラ
スとAl2O3とを約50wt%づつ混合した粉体10
0M量部に対してポリビニルブチラール10重量部、ジ
ブチルフタレート6重量部、イソプロピルアルコール3
9重量部、1−1−1ト’)クロルエタ720重景部を
加え24時間ボールミル混合を行いスラリを造った。こ
のスラリーをポリエステルフィルム上にドクターブレー
ド法にて塗布、乾燥し厚み100 Jimのグリーンシ
ートを作成し、充分なエージングを行なう。次にグリー
ンシートを適当なサイズに切断した後Ag/Pdペース
トをスクリーン印刷によりグリーンシート上へ形成する
。ペーストを乾燥後、上記グリーンシートを複数枚重ね
80℃の温度下で、200AIA彌の圧力で加圧し一体
化させる。次に外形を切断の後、900℃−−1時間に
て焼成し多層基板を得た。ここで用いた印刷パターンは
第4図(a)に示すように成形体の一方に内部導体が片
寄ったものである。さらQて使用した絶縁材料は6種類
(A、B、C,D、E)であシガラス軟化点はそれぞれ
下記の如くである。
Example (Example 1) Powder 10 prepared by mixing approximately 50 wt% each of B2O3-8iO2 glass with a particle size of 0.5 to 5 μm and Al2O3.
10 parts by weight of polyvinyl butyral, 6 parts by weight of dibutyl phthalate, 3 parts by weight of isopropyl alcohol per 0M part
9 parts by weight, 1-1-1 parts') Chloreta 720 heavy parts were added and mixed in a ball mill for 24 hours to prepare a slurry. This slurry was applied onto a polyester film using a doctor blade method, dried to form a green sheet with a thickness of 100 Jim, and sufficiently aged. Next, the green sheet is cut into a suitable size, and then Ag/Pd paste is formed on the green sheet by screen printing. After drying the paste, a plurality of the green sheets are stacked and pressed together at a temperature of 80° C. with a pressure of 200 AIA. Next, after cutting the outer shape, it was fired at 900° C. for 1 hour to obtain a multilayer substrate. The printed pattern used here is one in which the internal conductor is offset to one side of the molded body, as shown in FIG. 4(a). Furthermore, six types of insulating materials (A, B, C, D, and E) were used, and the glass softening points of each were as follows.

材料A −soo℃ z  B  −520℃ z  C−550℃ y  D  −600℃ z  E  −650℃ 内部導体はAglPd系でPdの含有率が0.10゜2
0.30重量%の4種数のペーストを用いた。
Material A -soo℃ z B -520℃ z C -550℃ y D -600℃ z E -650℃ The internal conductor is AglPd based with a Pd content of 0.10゜2
Four types of paste were used at 0.30% by weight.

4種数のペーストの収縮開始点は室側の結果、下記の如
くであった。
The shrinkage starting points of the four types of pastes on the chamber side were as follows.

1100A     −601℃9 0A g・10Pd −531℃8 0Ag−20Pd −568℃7 0A g・3oPd −614℃上記 のように作成した多層基について第9図シて示すように
、内部導体36を内蔵する部分の基板37の面方向収縮
率eE内部導体36を内蔵していない部分の基板37の
面方向方縮率lDを測定。
1100A -601℃9 0A g・10Pd -531℃8 0Ag-20Pd -568℃7 0A g・3oPd -614℃As shown in Fig. 9, the multilayer base made as above has an internal conductor 36 built-in. The in-plane shrinkage rate eE of the substrate 37 in the portion where the internal conductor 36 is not built-in is measured.

算出し、収縮率差Δ1(=lD−4E)を箕出し各材料
の組み合せにおける基板変形の度合を求めた。
The degree of substrate deformation in each material combination was determined by calculating the shrinkage rate difference Δ1 (=lD−4E).

結果を第1表に示す。第1表から絶縁材料のガラス軟化
点Tsが内部導体材料の収縮開始点よりも低温の場合、
収縮差Δ!は0であった。つまり基板変形は発生しなか
った。従ってAg/PdペーストのPd含有率をXとし
た時に、0式。
The results are shown in Table 1. From Table 1, if the glass softening point Ts of the insulating material is lower than the contraction start point of the internal conductor material,
Shrinkage difference Δ! was 0. In other words, no substrate deformation occurred. Therefore, when the Pd content of the Ag/Pd paste is set to X, the formula is 0.

Ts≦2. (x + 30)+464が成立すること
が確認された。
Ts≦2. It was confirmed that (x + 30) + 464 holds true.

第1表 (実施例2) 絶縁体材料に実施例1で用いた材料C(Ts=650°
Q)、Ag−Pd内部導体材料にsoAgaloPd(
収量開始点=631℃)を用いた。内部導体材料に絶縁
体材料Cを0〜20wt%含有させたものを内部導体と
した時の多層基板の変形度合を測定した。基板の製造方
法、評価方法は実施例1と同様である。結果を第2表に
示す。
Table 1 (Example 2) Material C used in Example 1 as the insulator material (Ts = 650°
Q), soAgaloPd (
Yield starting point = 631°C) was used. The degree of deformation of the multilayer substrate was measured when the internal conductor material contained 0 to 20 wt% of the insulating material C. The manufacturing method and evaluation method of the substrate are the same as in Example 1. The results are shown in Table 2.

第2表 第2表より内部導体材料(90Ag・1oPd)へ絶縁
材料Cを含有させた場合、含有量が5wt% 以上で焼
成収縮差Δlは0となり、基板変形は発生しなかった。
Table 2 From Table 2, when the internal conductor material (90Ag/1oPd) contained the insulating material C, the firing shrinkage difference Δl was 0 when the content was 5 wt% or more, and no substrate deformation occurred.

但し、含有量が5 wt%  を越えた場合、導体抵抗
値が15wt%の場合14mΩ/;。
However, if the content exceeds 5 wt%, the conductor resistance value is 14 mΩ/; if the conductor resistance value is 15 wt%.

20wt係 の場合、21.5mΩ/口と非常に大きく
なり実用に適さなかった。従って5〜10wt%の含有
量が適切であった。
In the case of a 20wt unit, the resistance was extremely large at 21.5mΩ/mouth, making it unsuitable for practical use. Therefore, a content of 5 to 10 wt% was appropriate.

(実施例3) 絶縁体材料に実施例1で用いた材料A(T3=500℃
)、Ag、Pd内部導体に1ooAg(焼成収縮開始点
=5o1℃)を用いた。内部導体材料中の導電性金属分
の含有量を50〜80wt%とじた内部導体を作成し、
各内部導体を用いた多層基板を実施例1と同じ方法で作
成、評価した結果を第3表に示す。
(Example 3) Material A used in Example 1 as an insulator material (T3 = 500°C
), Ag, Pd 1ooAg (firing shrinkage start point = 5o1°C) was used for the internal conductor. Create an internal conductor with a conductive metal content of 50 to 80 wt% in the internal conductor material,
A multilayer board using each internal conductor was produced and evaluated using the same method as in Example 1. Table 3 shows the results.

第3表 第3表より内部導体の導電性金属粉の含有率が了Owt
%を越える場合、焼成収縮差Δlは0でなくなシ基板変
形が発生してくる。但し、逆に55wt%未満の場合、
導体抵抗値が増加し実用に適さなかった。含有率が55
〜70wt%の場合、基板変形も発生せず又、導体抵抗
値も良好結果であった。
Table 3 From Table 3, the content of conductive metal powder in the internal conductor is Owt.
%, the firing shrinkage difference Δl is no longer 0 and deformation of the substrate occurs. However, if it is less than 55wt%,
The conductor resistance value increased, making it unsuitable for practical use. Content rate is 55
In the case of ~70 wt%, no substrate deformation occurred and the conductor resistance value was also good.

発明の効果 以上のように本発明によれば、1000℃で、かつ空気
中で焼成可能なセラミック多層基板が変形なしに容易に
製造できる。
Effects of the Invention As described above, according to the present invention, a ceramic multilayer substrate that can be fired at 1000° C. in air can be easily produced without deformation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はセラミック基板上での印刷多層法による多層基
板の製造プロセスを示すフローチャート、第2図はグリ
ーンシート上での印刷多層法による多層基板の製造プロ
セスを示すフローチャート、第3図はグリーンシート多
層法による多層基板の製造プロセスを示すフローチャー
ト、第4図は焼成時の基板変形を示し、(a)は焼成前
の状態を示す概略図、■)は焼成後の状態を示す概略図
、第5図。 第6図、第7図は導体、絶縁体の収縮曲線を示すグラフ
、第8図はAg/Pdペーストの組成による収縮開始点
を示すグラフ、第9図は焼成変形を測定するための多層
基板を示す概略図である。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第 2 図 第3図 第4図 温A□ 第8図
Figure 1 is a flowchart showing the manufacturing process of a multilayer board using the printed multilayer method on a ceramic substrate, Figure 2 is a flowchart showing the manufacturing process of a multilayer board using the printed multilayer method on a green sheet, and Figure 3 is a green sheet. Flowchart showing the manufacturing process of a multilayer board by the multilayer method, Figure 4 shows the deformation of the board during firing, (a) is a schematic diagram showing the state before firing, ■) is a schematic diagram showing the state after firing, Figure 5. Figures 6 and 7 are graphs showing shrinkage curves of conductors and insulators, Figure 8 is a graph showing shrinkage start points depending on the composition of Ag/Pd paste, and Figure 9 is a multilayer substrate for measuring firing deformation. FIG. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4 Temperature A□ Figure 8

Claims (3)

【特許請求の範囲】[Claims] (1)セラミック絶縁体と導体とが交互に重なり複数の
層を形成するセラミック多層基板において、このセラミ
ック絶縁体は1000℃以下で焼結するガラスセラミッ
クスであり、導体はAgとPdの少なくとも1種からな
り、導体の組成を(100−x)Ag、x・Pd(但し
xはPdの重量%で0≦x≦30)とした場合、前記ガ
ラスセラミックスのガラス軟化点TsがTs≦1/24
(x+30)^2+464〔℃〕となることを特徴とす
るセラミック多層基板。
(1) In a ceramic multilayer board in which ceramic insulators and conductors are alternately stacked to form a plurality of layers, the ceramic insulator is a glass ceramic that is sintered at 1000°C or less, and the conductor is at least one of Ag and Pd. When the composition of the conductor is (100-x)Ag, x・Pd (where x is the weight% of Pd and 0≦x≦30), the glass softening point Ts of the glass ceramic is Ts≦1/24.
(x+30)^2+464 [°C].
(2)セラミック絶縁体と導体とが交互に重なり複数の
層を形成するセラミック多層基板において、このセラミ
ック絶縁体は1000℃以下で焼結するガラスセラミッ
クスであり、ガラス軟化点がセラミック絶縁体のそれと
同等か、あるいはそれ以上である無機材料を6〜10重
量%含有する導体を用いることを特徴とするセラミック
多層基板。
(2) In a ceramic multilayer board in which ceramic insulators and conductors are alternately stacked to form multiple layers, the ceramic insulator is a glass ceramic that is sintered at 1000°C or less, and the glass softening point is similar to that of the ceramic insulator. A ceramic multilayer board characterized by using a conductor containing 6 to 10% by weight of an inorganic material equal to or greater than that.
(3)セラミック絶縁体と導体とが交互に重なり複数の
層を形成するセラミック多層基板において、このセラミ
ック絶縁体は1000℃以下で焼結するガラスセラミッ
クスであり導電性金属、有機バインダー、有機溶剤等か
らなる導体において導電性金属の含有率が56〜70重
量%であることを特徴とするセラミック多層基板。
(3) In a ceramic multilayer board in which ceramic insulators and conductors are alternately stacked to form multiple layers, the ceramic insulators are glass ceramics that are sintered at 1000°C or less, and conductive metals, organic binders, organic solvents, etc. A ceramic multilayer substrate characterized in that the content of conductive metal in the conductor is 56 to 70% by weight.
JP61208285A 1986-09-04 1986-09-04 Ceramic multilayer board Expired - Lifetime JPH0797703B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61208285A JPH0797703B2 (en) 1986-09-04 1986-09-04 Ceramic multilayer board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61208285A JPH0797703B2 (en) 1986-09-04 1986-09-04 Ceramic multilayer board

Publications (2)

Publication Number Publication Date
JPS6364399A true JPS6364399A (en) 1988-03-22
JPH0797703B2 JPH0797703B2 (en) 1995-10-18

Family

ID=16553714

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61208285A Expired - Lifetime JPH0797703B2 (en) 1986-09-04 1986-09-04 Ceramic multilayer board

Country Status (1)

Country Link
JP (1) JPH0797703B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0464281A (en) * 1990-07-04 1992-02-28 Hitachi Ltd Manufacture of ceramic multilayer board

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51127112A (en) * 1975-04-30 1976-11-05 Fujitsu Ltd Method of producing multiilayered glass substrate
JPS599992A (en) * 1982-07-08 1984-01-19 株式会社日立製作所 Method of producing multilayer circuit board
JPS6028296A (en) * 1983-07-27 1985-02-13 株式会社日立製作所 Ceramic multilayer printed circuit board
JPS6070799A (en) * 1983-09-28 1985-04-22 株式会社日立製作所 Composition for through hole conductor of glass ceramic multilayer circuit board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51127112A (en) * 1975-04-30 1976-11-05 Fujitsu Ltd Method of producing multiilayered glass substrate
JPS599992A (en) * 1982-07-08 1984-01-19 株式会社日立製作所 Method of producing multilayer circuit board
JPS6028296A (en) * 1983-07-27 1985-02-13 株式会社日立製作所 Ceramic multilayer printed circuit board
JPS6070799A (en) * 1983-09-28 1985-04-22 株式会社日立製作所 Composition for through hole conductor of glass ceramic multilayer circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0464281A (en) * 1990-07-04 1992-02-28 Hitachi Ltd Manufacture of ceramic multilayer board

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