JPH0464281A - Manufacture of ceramic multilayer board - Google Patents
Manufacture of ceramic multilayer boardInfo
- Publication number
- JPH0464281A JPH0464281A JP2175225A JP17522590A JPH0464281A JP H0464281 A JPH0464281 A JP H0464281A JP 2175225 A JP2175225 A JP 2175225A JP 17522590 A JP17522590 A JP 17522590A JP H0464281 A JPH0464281 A JP H0464281A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic multilayer
- manufacturing
- firing
- conductor
- shrink
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000004020 conductor Substances 0.000 claims abstract description 31
- 238000003475 lamination Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 23
- 239000011521 glass Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 4
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052863 mullite Inorganic materials 0.000 claims description 3
- 238000010276 construction Methods 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims 1
- 229910052750 molybdenum Inorganic materials 0.000 claims 1
- 229910052763 palladium Inorganic materials 0.000 claims 1
- 238000010304 firing Methods 0.000 abstract description 35
- 238000010030 laminating Methods 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 3
- 230000006399 behavior Effects 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- 239000011230 binding agent Substances 0.000 description 6
- 239000002904 solvent Substances 0.000 description 5
- 239000010410 layer Substances 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- 239000012298 atmosphere Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 239000002002 slurry Substances 0.000 description 3
- LRHPLDYGYMQRHN-UHFFFAOYSA-N N-Butanol Chemical compound CCCCO LRHPLDYGYMQRHN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 2
- 238000007606 doctor blade method Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 239000004014 plasticizer Substances 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000001856 Ethyl cellulose Substances 0.000 description 1
- ZZSNKZQZMQGXPY-UHFFFAOYSA-N Ethyl cellulose Chemical compound CCOCC1OC(OC)C(OCC)C(OCC)C1OC1C(O)C(O)C(OC)C(CO)O1 ZZSNKZQZMQGXPY-UHFFFAOYSA-N 0.000 description 1
- AEMRFAOFKBGASW-UHFFFAOYSA-M Glycolate Chemical compound OCC([O-])=O AEMRFAOFKBGASW-UHFFFAOYSA-M 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- CYTYCFOTNPOANT-UHFFFAOYSA-N Perchloroethylene Chemical group ClC(Cl)=C(Cl)Cl CYTYCFOTNPOANT-UHFFFAOYSA-N 0.000 description 1
- XSTXAVWGXDQKEL-UHFFFAOYSA-N Trichloroethylene Chemical group ClC=C(Cl)Cl XSTXAVWGXDQKEL-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 125000000484 butyl group Chemical group [H]C([*])([H])C([H])([H])C([H])([H])C([H])([H])[H] 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229920001249 ethyl cellulose Polymers 0.000 description 1
- 235000019325 ethyl cellulose Nutrition 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 125000001557 phthalyl group Chemical group C(=O)(O)C1=C(C(=O)*)C=CC=C1 0.000 description 1
- 229920002037 poly(vinyl butyral) polymer Polymers 0.000 description 1
- 229920006267 polyester film Polymers 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229950011008 tetrachloroethylene Drugs 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、導体部を形成したグリーンシートを複数枚積
層して焼成するセラミック多層基板の作製法において、
特に1寸法精度に優れたセラミック多層基板を得る製造
方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a ceramic multilayer substrate in which a plurality of green sheets each having a conductor portion formed thereon are laminated and fired.
In particular, the present invention relates to a manufacturing method for obtaining a ceramic multilayer substrate with excellent one-dimensional accuracy.
近年、LSI等の集積回路の高速化、高密度化に伴い、
セラミック基板上に、直接、あるいは、チップキャリア
を介してこれらの半導体素子を実装することで、実装部
分の高速化を図る試みがなされるようになってきた。而
も、LSI等の集積化が更に進むにつれて、これら半導
体素子の大型化とともに、セラミック基板の方も、微細
配線化。In recent years, with the increase in speed and density of integrated circuits such as LSI,
Attempts have been made to increase the speed of the mounting portion by mounting these semiconductor elements on a ceramic substrate directly or via a chip carrier. However, as the integration of LSIs and other devices progresses, these semiconductor elements become larger and ceramic substrates also become finer in their wiring.
多層化、大型化が進められるようになった。このような
セラミック多層基板は、一般に、グリーンシート積層法
により作られる。その作製法は以下のようなものである
。はじめに、セラミック原料粉、及び、それを相互に密
着させるバインダ(熱可塑性樹脂)、及び、可塑剤等を
、バインダを溶かす適当な溶媒中に投入・混合して、ス
ラリを調製する。次に、脱泡処理により、取り込まれた
気泡の除去、及び、粘度調整を行った後、ドクターブレ
ード法等によりシート状に成形する。最後に乾燥により
溶媒を飛散させてグリーンシートを得る。グリーンシー
トはパンチ等で所定のスルーホール加工を施した後、ス
ルーホールへの導体充填、及び、シート表面への所定の
導体配線形成等を行う。このようにして得られたシート
を、位置ずれが起きないように工夫をして、所定の枚数
重ねて、ホットプレスにより加熱圧着して積層体を作製
する。最後に、導体配線が酸化しないような、焼成プロ
ファイル、雰囲気下で焼成し、セラミック多層基板を得
る。Multi-layered and larger devices have become more common. Such ceramic multilayer substrates are generally made by a green sheet lamination method. The manufacturing method is as follows. First, a slurry is prepared by adding and mixing ceramic raw material powder, a binder (thermoplastic resin) that makes them adhere to each other, a plasticizer, etc. in a suitable solvent that dissolves the binder. Next, a defoaming process is performed to remove trapped air bubbles and to adjust the viscosity, and then it is formed into a sheet by a doctor blade method or the like. Finally, the solvent is scattered by drying to obtain a green sheet. After the green sheet is processed with predetermined through holes using a punch or the like, the through holes are filled with conductors, and predetermined conductor wiring is formed on the surface of the sheet. A predetermined number of sheets obtained in this manner are stacked one on top of the other, taking care not to cause any positional shift, and are heat-pressed and bonded using a hot press to produce a laminate. Finally, the ceramic multilayer substrate is obtained by firing under an atmosphere with a firing profile that does not oxidize the conductor wiring.
ところで、このようなセラミック多層基板の作製に当た
って、要求されることの一つに寸法精度がある。これは
、半導体素子の集積化に伴う半導体素子のセラミック基
板の接続点の高密度化や、基板の大型化によって、不可
欠の要求となってきた。寸法精度を向上するには、焼成
収納率を制御することが必要である。焼成収縮率は、原
料の精度分布やプロセス条件等によって大きく変化し、
それらの制御・管理が重要であることは広く知られてい
る。しかし、実際のセラミック多層基板は、導体部と絶
縁部の間に、積層時の変形特性や焼成収縮率等に差があ
るため、焼成時に収縮率の異常や、反り、凹凸等の問題
を生じることがあった。Incidentally, when producing such a ceramic multilayer substrate, one of the requirements is dimensional accuracy. This has become an indispensable requirement due to the increased density of connection points on ceramic substrates of semiconductor devices and the increased size of the substrates as semiconductor devices become more integrated. In order to improve dimensional accuracy, it is necessary to control the firing storage rate. The firing shrinkage rate varies greatly depending on the accuracy distribution of raw materials, process conditions, etc.
It is widely known that their control and management are important. However, in actual ceramic multilayer substrates, there are differences in deformation characteristics during lamination and firing shrinkage between the conductor and insulating parts, resulting in problems such as abnormal shrinkage, warping, and unevenness during firing. Something happened.
これらの問題に対し、幾つかの試みが成されている。特
開昭60−137884号、特開昭62−260777
号等では、焼成時に、多層基板を両側からはさんで圧力
を加えることで、水平方向の収縮や、変形。Several attempts have been made to address these problems. JP 60-137884, JP 62-260777
No. 1, etc., the multilayer substrate is sandwiched from both sides and pressure is applied during firing, causing horizontal contraction and deformation.
反り等を抑える試みが報告されている。また、特開昭6
1−90448号公報では、隣接するグリーンシートの
導体配線を、逆向きにスキージを動かしてスクリーン印
刷することで、収縮率偏差の小さな、高精度で高密度な
セラミック多層基板を作製する試みが成されている。更
に、特開昭62−35659号公報では、導体配線領域
の外側に追加のグリーンシートを適量はさんで積層する
ことで、焼結中、基板全体にわたり、−様な収縮を与え
るとともに。Attempts to suppress warpage, etc. have been reported. Also, JP-A-6
1-90448, an attempt was made to fabricate a highly accurate, high-density ceramic multilayer substrate with small shrinkage rate deviation by screen printing conductor wiring on adjacent green sheets by moving a squeegee in the opposite direction. has been done. Furthermore, in Japanese Patent Application Laid-Open No. 62-35659, by sandwiching and laminating an appropriate amount of additional green sheets outside the conductor wiring area, --like shrinkage is applied to the entire substrate during sintering.
反りが無く元の幾何学形状が保存されるようなセラミッ
ク多層基板の製造法が報告されている。A method for manufacturing ceramic multilayer substrates that does not warp and preserves its original geometry has been reported.
上記従来技術は、しかし、前述した焼成収縮率異常等を
抑制するのに必ずしも充分ではない。基板の上下から圧
力をかけて焼結する手法は、改善がなされない場合もあ
るし、また、脱バインダがスムーズに行われないことも
ある。導体配線の印刷方向を調整する手法は、−船釣で
はない。導体配線領域の外側に追加のグリーンシートを
挿入する手法も、効果はあるが充分ではないことも多く
、また、追加分量の決定が難しい。However, the above-mentioned conventional technology is not necessarily sufficient to suppress the above-mentioned firing shrinkage rate abnormality. The method of sintering by applying pressure from above and below the substrate may not provide any improvement, and may not remove the binder smoothly. The method of adjusting the printing direction of conductor wiring is not a fishing boat. Inserting additional green sheets outside the conductor wiring area is also effective, but is often not sufficient, and it is difficult to determine the amount of additional green sheets.
本発明の目的は、このような導体部と絶縁部の積層時の
変形挙動や、収縮率の違い等によって生しる収縮率の偏
差・異常を減じないしは、補償することにある。An object of the present invention is to reduce or compensate for deviations and abnormalities in shrinkage rates caused by such deformation behavior during lamination of a conductor part and an insulating part, and differences in shrinkage rates.
本発明は、上記目的を達成するため、焼成時に−様な収
縮、パターンの相似的な変化を期待するのではなく、こ
れらの変形挙動を予め予見、乃至実験で確認して、それ
をスルーホール加工位置や、配線パターンの設計に反映
させることで、焼成後の基板内の導体配線の寸法精度を
向上させるようにしたものである。これは−見困難に思
えるが。In order to achieve the above object, the present invention does not expect similar shrinkage or similar changes in patterns during firing, but rather predicts or experimentally confirms these deformation behaviors, and then determines the deformation behavior through the through-hole. By reflecting this in the processing position and the design of the wiring pattern, the dimensional accuracy of the conductor wiring within the substrate after firing is improved. This seems difficult to see.
配線パターンや製造プロセスが決まれば、変形挙動は比
較的安定しており、実現が可能である。この手法は、導
体層と絶縁層の材料系が寄らず成立するが、その場合、
場合に応じて、当然、設計への反映の仕方は異なる。Once the wiring pattern and manufacturing process are determined, the deformation behavior is relatively stable and can be realized. This method works without the material systems of the conductive layer and the insulating layer being close to each other, but in that case,
Naturally, the way this is reflected in the design differs depending on the case.
本発明は、上述したように、スルーホール加工位置や配
線パターンの設計をする際に、積層・焼成時の変形挙動
を予め予測して、それを設計・施工に取り入れることで
、焼成後に寸法精度の良いセラミック多層基板を得るも
のである。As mentioned above, the present invention enables dimensional accuracy after firing by predicting deformation behavior during lamination and firing in advance and incorporating it into design and construction when designing through-hole processing positions and wiring patterns. A ceramic multilayer substrate with good quality can be obtained.
以下、本発明の実施例を図を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
〈実施例1〉
はじめに、グリーンシート作製の一例、及び、基板作製
の流れを提示した後、本発明の実施例を示す。<Example 1> First, an example of green sheet production and a flow of substrate production will be presented, and then an example of the present invention will be described.
平均粒径3.0μmのムライト粉70重量部。70 parts by weight of mullite powder with an average particle size of 3.0 μm.
シリカを主成分とするガラス粉(平均粒径1.2μm)
30重量部をボールミルに投入し、更に、バインダとし
て重合度1000のポリビニルブチラール6.5重量部
、可塑剤としてブチルフタリルグリコール酸ブチル2.
1重量部を加え、溶剤としては、トリクロルエチレン、
テトラクロルエチレン、n−ブタノールの三成分系溶剤
を投入して、湿式混合を二十四時間行うことで、スラリ
を調製した。このスラリを真空に引くことで、脱泡処理
、粘度調整を施す。これをドクターブレード法等により
、シリコンコート処理を施したポリエステルフィルム上
に、均一の厚さで塗布して、次に、乾燥炉を通して溶剤
を飛散させて、厚さ約0.25mnのグリーンシートを
得た。Glass powder mainly composed of silica (average particle size 1.2μm)
30 parts by weight were added to a ball mill, and 6.5 parts by weight of polyvinyl butyral with a degree of polymerization of 1000 was added as a binder, and 2.5 parts by weight of butyl phthalyl glycolate were added as a plasticizer.
1 part by weight was added, and as a solvent, trichlorethylene,
A slurry was prepared by adding a three-component solvent of tetrachloroethylene and n-butanol and performing wet mixing for 24 hours. This slurry is vacuumed to perform defoaming treatment and viscosity adjustment. This is applied to a uniform thickness on a polyester film treated with silicone using a doctor blade method, etc., and then the solvent is scattered through a drying oven to form a green sheet with a thickness of about 0.25 mm. Obtained.
このグリーンシートを所定の大きさ、ここでは200
m X 200閣の大きさに切断した後、パンチ法によ
り所定位置にスルーホールをあける。このスルーホール
、及び、シートの表面に、W粉末とエチルセルロース等
のバインダ及び少量の有機溶剤で調製した導体ペースト
を、スクリーン印刷法により印刷することで、層間接続
のためのビアホール及び、所定の回路パターンを形成す
ることができる。This green sheet is set to a predetermined size, here 200.
After cutting to a size of 200 m x 200 m, through holes are punched at predetermined positions using the punch method. By printing a conductive paste prepared with W powder, a binder such as ethyl cellulose, and a small amount of organic solvent on the through holes and the surface of the sheet using a screen printing method, via holes for interlayer connection and a predetermined circuit are printed. A pattern can be formed.
これらのグリーンシートを、ガイド穴の位置を合わせて
四十四枚積層し、次に、ホットプレス装置で、120℃
、100kgf/Jで15分間積層圧着することで、セ
ラミック積層体を作製する。Forty-four of these green sheets were stacked with the guide holes aligned, and then heated at 120°C using a hot press machine.
, 100 kgf/J for 15 minutes to produce a ceramic laminate.
この積層体を焼成炉内に入れ、約20溶量%の水素を含
む窒素雰囲気中で焼成する。その際、昇温過程では、更
に、少量の水蒸気を含む雰囲気下で、80〜b
昇温することでバインダを除去し、最高温度1640℃
に達した後は、水蒸気は除去し、この温度で1.5時間
保持して焼結体を得る。還元性雰囲気で焼成するのは、
配線導体の金属、ここではWの配化を防ぐためである。This laminate is placed in a firing furnace and fired in a nitrogen atmosphere containing about 20% hydrogen by volume. At that time, in the temperature raising process, the binder was removed by further increasing the temperature by 80 to 80℃ in an atmosphere containing a small amount of water vapor, and the maximum temperature was 1640℃.
After reaching this temperature, the water vapor is removed and the temperature is maintained for 1.5 hours to obtain a sintered body. Firing in a reducing atmosphere is
This is to prevent the metal of the wiring conductor, here W, from being disposed.
以上のようにしてセラミック多層基板を作製するが、基
板の種類や、導体ペーストの種類等により、第2図や第
4図のような歪んだ形で収縮するものが多数見られた。Ceramic multilayer substrates are produced as described above, but many of them shrink in distorted shapes as shown in FIGS. 2 and 4, depending on the type of substrate, the type of conductive paste, etc.
尚、図面では歪みを強肩して表している。ここで、1は
焼成前の積層体、2は焼成後の焼結体を表す。また、1
1及び21は、それぞれ、焼成前後のチップエリア(L
SIチップを搭載する部分)で、非常に多数のビアホー
ルが形成されている。一方、12、及び、22は、それ
ぞれ焼成前後の白板部を表し、この部分には、表面パッ
ドはもとより、ビアホールも無く、内層の電源配線や信
号配線、裏面パッドが少々あるだけである。このような
歪んだ形の収縮は、この白板部(セラミック絶縁部)と
導体部の積層時の変形9診動や収縮率及びその異方性の
違い、あるいは、収縮開始温度の違い等に、その主要な
原因がある。ところでこのような歪んだ形の収縮挙動は
、セラミック基板及び導体ペーストの種類・組成・原料
粒径・調製法等を同一とし、また、多層基板の回路構成
・寸法が一定であれば、はぼ、再現性のある収縮挙動を
示す。そこで本発明では、これらの変形挙動を予め予見
、乃至実験で確認して、それをスルーホール加工位置や
配線パターンの設計に反映させることで、焼成後の基板
内の導体配線の寸法精度を向上させることが可能となる
。It should be noted that in the drawings, the distortion is emphasized. Here, 1 represents the laminate before firing, and 2 represents the sintered body after firing. Also, 1
1 and 21 are chip areas (L) before and after firing, respectively.
A large number of via holes are formed in the area where the SI chip is mounted. On the other hand, 12 and 22 represent the white plate parts before and after firing, respectively, and these parts have no surface pads or via holes, and only have inner layer power wiring, signal wiring, and a few back pads. This distorted form of shrinkage is due to the deformation during lamination of the white plate part (ceramic insulating part) and the conductor part, the difference in the shrinkage rate and its anisotropy, or the difference in the shrinkage start temperature. There is a major reason for this. By the way, such distorted shrinkage behavior is almost impossible if the type, composition, raw material particle size, preparation method, etc. of the ceramic substrate and conductive paste are the same, and if the circuit configuration and dimensions of the multilayer substrate are constant. , exhibiting reproducible shrinkage behavior. Therefore, in the present invention, these deformation behaviors are predicted in advance or confirmed through experiments, and this is reflected in the through-hole processing position and wiring pattern design, thereby improving the dimensional accuracy of the conductor wiring in the board after firing. It becomes possible to do so.
第1図は、第2図のように太鼓状に歪んで収縮する場合
に、その歪み具合を予め求めて、焼成後にチップエリア
が規則正しく配列し、且つ、各エリアが正方形状に寸法
精度良く仕上がるよう、回路パターンを形成する手法を
示した。第1図表図のようなパターンを形成するのには
若干の手間はかかるが、コンピュータ制御で孔開け、パ
ターン設計をしており、充分可能であり、寸法精度の向
上に大いに有効である。Figure 1 shows that when the shrinkage occurs in a drum-like shape as shown in Figure 2, the degree of distortion is determined in advance so that the chip areas are regularly arranged after firing and each area is finished in a square shape with high dimensional accuracy. We demonstrated a method for forming circuit patterns. It takes some effort to form a pattern like the one shown in Figure 1, but since the holes are drilled and the pattern is designed under computer control, it is possible and very effective in improving dimensional accuracy.
第3図は、第4図のように鼓状に歪んで収縮する場合に
、その歪み具合を予め求めて、焼成後にチップエリアが
規則正しく配列し、且つ、各エリアが正方形状に寸法精
度良く仕上がるよう、回路パターンを形成する手法を示
したもので、やはり寸法精度の向上に有効である。Figure 3 shows that when the shrinkage is distorted into a drum shape as shown in Figure 4, the degree of distortion is determined in advance so that after firing, the chip areas are arranged regularly and each area is finished in a square shape with high dimensional accuracy. This method shows a method for forming a circuit pattern, which is also effective in improving dimensional accuracy.
本実施例では、セラミック基板材料にムライト−ガラス
系、配線導体材料はWの例を示したが、本手法は勿論、
この系に限定されるものではない。In this example, the ceramic substrate material is mullite-glass, and the wiring conductor material is W.
It is not limited to this system.
例えば、セラミック基板材料として、アルミナ系。For example, alumina is used as a ceramic substrate material.
アルミナガラス系、ムライト系、配線導体材料としてW
またはMOを用いた場合には、はぼ、同様の製造・焼成
プロセスにより、多層基板の作製が可能であり、上述と
同様の歪んだ形での収縮の問題に関し、本手法の適用が
可能である。Alumina glass type, mullite type, W as wiring conductor material
Alternatively, when MO is used, it is possible to fabricate a multilayer substrate through the same manufacturing and firing process, and this method can be applied to the problem of shrinkage in a distorted form similar to the above. be.
又、高熱伝導性の窒化アルミニウム系のセラミック基板
材料を用いた場合、配線導体にはやはりWまたはMOを
使用し、焼成温度を1800〜2000’Cにすること
で、多層基板の作製が可能であるが、やはり本手法を適
用することができる。Furthermore, when using a highly thermally conductive aluminum nitride-based ceramic substrate material, it is possible to create a multilayer substrate by using W or MO for the wiring conductor and by setting the firing temperature to 1800 to 2000'C. However, this method can still be applied.
更に、低誘電率のガラスをセラミック基板材料とし、低
抵抗のCu、あるいは、空気中焼成が可能なAg−Pd
、Ag−Ptを導体材料とする低温焼成基板についても
、本手法の適用が可能である。Furthermore, we use low dielectric constant glass as a ceramic substrate material, low resistance Cu, or Ag-Pd that can be fired in air.
The present method can also be applied to low-temperature fired substrates using Ag-Pt as a conductive material.
〈実施例2〉
上述したような材料系を用いて、セラミック多層基板を
作製する場合に、部分的に導体配線やビアホールが稠密
に集中しであるような回路パターンの場合、その部分の
み大きく収縮して、全体として歪んだ形で収縮すること
がある。このような場合も、実施例1と同様に、その変
形挙動を予め予見乃至実験で確認して、それをスルーホ
ール加工位置や配線パターンの設計に反映させることで
、焼成後の基板内の導体配線の寸法精度を向上させるこ
とができる。〈Example 2〉 When manufacturing a ceramic multilayer board using the material system described above, if the circuit pattern has conductor wiring or via holes densely concentrated in some parts, only those parts will shrink significantly. As a result, the entire structure may shrink in a distorted manner. In such a case, as in Example 1, by confirming the deformation behavior in advance through prediction or experiment, and reflecting it in the design of the through-hole processing position and wiring pattern, the conductor inside the board after firing can be adjusted. The dimensional accuracy of wiring can be improved.
第6図は、このような改善策を施さない場合の、焼成前
後の寸法変化を示したもので、第5図は改善策を施した
場合を例示したものである。前例と同様に、図中1は焼
成前の積層体を、2は焼成後の焼結体を表す。12及び
22は、それぞれ焼成前後の白板部を表す。また、11
及び21は、それぞれ焼成前後の通常のチップエリアを
表す。本例では更に、大面積で、且つ、稠密な配置を施
したエリアがある(図中13及び23)。やはり、白板
部と導体部の収縮率等の違い等から、第6図のように歪
んだ形で収縮する例が多く見られた。FIG. 6 shows the dimensional changes before and after firing without such improvement measures, and FIG. 5 shows an example of the case with improvement measures. As in the previous example, 1 in the figure represents the laminate before firing, and 2 represents the sintered body after firing. 12 and 22 represent the white plate portions before and after firing, respectively. Also, 11
and 21 represent normal chip areas before and after firing, respectively. In this example, there are further areas (13 and 23 in the figure) that have a large area and are densely arranged. As expected, due to the difference in shrinkage rate between the white plate part and the conductor part, there were many cases where the shrinkage occurred in a distorted manner as shown in FIG. 6.
本例でも、このような変形挙動を予め予見、ないし実験
で確認して、それをスルーホール加工位置や配線パター
ンの設計に反映させることで、第5図に示すように、焼
成後にチップエリアを規則正しく配列させ、而も各エリ
アを正方形状に、寸法精度良く仕上げることが可能であ
る。In this example as well, by predicting or experimentally confirming such deformation behavior in advance and reflecting it in the design of through-hole processing positions and wiring patterns, the chip area can be changed after firing as shown in Figure 5. It is possible to arrange them regularly and finish each area in a square shape with high dimensional accuracy.
本実施例でも、前例で示したような種々の材料系に対し
て有効である。This embodiment is also effective for various material systems as shown in the previous example.
〈実施例3〉
実施例1で述べたような基板の焼成において、基板全体
の大きな異形が現れない場合でも、ビアホールの稠密に
形成されたチップエリアの収縮率が、白板部の収縮率よ
り0.2〜0.5%はど高い場合が見られた。このよう
な寸法を予め、設計時に補償してもよい。このような補
償は、配線パターンに大きな異形が見られる場合も、必
要とされる事が多い。<Example 3> In the firing of the substrate as described in Example 1, even if no large irregularities appear on the entire substrate, the shrinkage rate of the chip area where the via holes are densely formed is 0 compared to the shrinkage rate of the white plate part. In some cases, it was as high as .2 to 0.5%. Such dimensions may be compensated for in advance during design. Such compensation is often required even when large irregularities are observed in the wiring pattern.
本発明によれば、ビアホールや導体配線層を形成したグ
リーンシートを複数枚積層して焼成するセラミック多層
基板の作製方法で、導体部とセラミック絶縁部の積層時
の変形特性や焼成収縮率の違い等によって生じる歪みや
異形の影響を抑え、あるいは、補償するために、この歪
みや異形を予め想定、あるいは、実験で確めて、配線パ
ターン等に反映することで、寸法精度の良いセラミック
多層基板を得ることができる。この結果、配線密度の高
い、高信頼性のセラミック多層基板の製造が可能となる
。また本手法は、種々の材料系について有効である。According to the present invention, there is a method for manufacturing a ceramic multilayer board in which a plurality of green sheets on which via holes and conductor wiring layers are formed are laminated and fired, and the difference in deformation characteristics and firing shrinkage rate during lamination of conductor parts and ceramic insulating parts is achieved. In order to suppress or compensate for the effects of distortions and irregularities caused by such factors, we can create ceramic multilayer boards with good dimensional accuracy by assuming these distortions and irregularities in advance or confirming them through experiments and reflecting them in wiring patterns, etc. can be obtained. As a result, it becomes possible to manufacture a highly reliable ceramic multilayer substrate with high wiring density. Furthermore, this method is effective for various material systems.
第1図は、本発明の一実施例の焼成前後の配線パターン
の説明図、第2図は、第1図で、本発明を適用しなかっ
た場合の説明図、第3図および第5図もそれぞれ、本発
明の一実施例であり、第3図と第4図、第5図と第6図
がそれぞれ、第1図と第2図の関係に準する。
1・・焼成前の積層体、2・・・焼結体、11・・・積
層体のチップエリア、12・・・積層体の白板部、13
・・積層体の大面積接続エリア、21・・焼結体のチッ
プエリア、22・・・焼結体の白板部、23・・・焼結
体箱
図FIG. 1 is an explanatory diagram of the wiring pattern before and after firing according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of the wiring pattern in the case where the present invention is not applied to FIG. 1, and FIGS. 3 and 5. 3 and 4, and FIG. 5 and FIG. 6 respectively correspond to the relationship in FIG. 1 and FIG. 2, respectively. DESCRIPTION OF SYMBOLS 1... Laminate before firing, 2... Sintered body, 11... Chip area of laminate, 12... White plate part of laminate, 13
...Large area connection area of the laminate, 21...Chip area of the sintered body, 22...White plate part of the sintered body, 23...Sintered body box diagram
Claims (4)
導体材料を埋め込む工程、及び/あるいは、シート表面
に導体配線を作成する工程により得られたシートを、複
数枚積層して焼成するセラミツク多層基板の製造方法に
おいて、 水平方向に対し、導体部と絶縁部の収縮率の違い等を予
め考慮し、更に、積層時の変形挙動等も考慮して、スル
ーホール加工位置、及び/あるいは表面導体配線パター
ンを設計・施工することを特徴とするセラミツク多層基
板の製造方法。1. In a method for manufacturing a ceramic multilayer board, in which a plurality of sheets obtained by processing through-holes in a green sheet and embedding a conductive material therein, and/or a step of creating conductor wiring on the surface of the sheet are laminated and fired. , The through-hole processing position and/or the surface conductor wiring pattern should be designed by considering in advance the difference in shrinkage rate between the conductor part and the insulating part in the horizontal direction, as well as the deformation behavior during lamination. 1. A method for manufacturing a ceramic multilayer substrate, characterized by:
半導体実装部分の想定収縮率を、基板全体の想定収縮率
とは異なる値として、設計・施工を行うセラミツク多層
基板の製造方法。2. 2. The method of manufacturing a ceramic multilayer board according to claim 1, wherein the design and construction are performed by setting the assumed shrinkage rate of the semiconductor mounting portion in which the via holes are densely formed to a value different from the assumed shrinkage rate of the entire board.
ルミナーガラス,ムライト,ムライト−ガラス、あるい
は、窒化アルミニウムのいずれかであり、導体層はWま
たはMoを用いたセラミツク多層基板の製造方法。3. 3. The method of manufacturing a ceramic multilayer substrate according to claim 1, wherein the insulating layer is made of alumina, alumina glass, mullite, mullite-glass, or aluminum nitride, and the conductor layer is made of W or Mo.
ス、または、低誘電率ガラスとセラミツクスの複合物で
あり、導体層はCu,Ag−Pd、または、Ag−Pt
を用いたセラミツク多層基板の製造方法。4. In claim 1 or 2, the insulating layer is made of low dielectric constant glass or a composite of low dielectric constant glass and ceramics, and the conductive layer is made of Cu, Ag-Pd, or Ag-Pt.
A method for manufacturing a ceramic multilayer substrate using
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2175225A JPH0828579B2 (en) | 1990-07-04 | 1990-07-04 | Method for manufacturing ceramic multilayer substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2175225A JPH0828579B2 (en) | 1990-07-04 | 1990-07-04 | Method for manufacturing ceramic multilayer substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0464281A true JPH0464281A (en) | 1992-02-28 |
JPH0828579B2 JPH0828579B2 (en) | 1996-03-21 |
Family
ID=15992477
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2175225A Expired - Lifetime JPH0828579B2 (en) | 1990-07-04 | 1990-07-04 | Method for manufacturing ceramic multilayer substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0828579B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0697661A (en) * | 1992-09-11 | 1994-04-08 | Sumitomo Kinzoku Ceramics:Kk | Manufacture of ceramics multi-layer substrate |
JP2011096821A (en) * | 2009-10-29 | 2011-05-12 | Murata Mfg Co Ltd | Method of manufacturing ceramic substrate |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62272588A (en) * | 1986-05-21 | 1987-11-26 | 株式会社日立製作所 | Manufacture of multilayer ceramic interconnection board |
JPS6364399A (en) * | 1986-09-04 | 1988-03-22 | 松下電器産業株式会社 | Ceramic multilayer board |
JPS63227097A (en) * | 1987-03-17 | 1988-09-21 | 富士通株式会社 | Method of thick film through-hole land |
-
1990
- 1990-07-04 JP JP2175225A patent/JPH0828579B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62272588A (en) * | 1986-05-21 | 1987-11-26 | 株式会社日立製作所 | Manufacture of multilayer ceramic interconnection board |
JPS6364399A (en) * | 1986-09-04 | 1988-03-22 | 松下電器産業株式会社 | Ceramic multilayer board |
JPS63227097A (en) * | 1987-03-17 | 1988-09-21 | 富士通株式会社 | Method of thick film through-hole land |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0697661A (en) * | 1992-09-11 | 1994-04-08 | Sumitomo Kinzoku Ceramics:Kk | Manufacture of ceramics multi-layer substrate |
JP2011096821A (en) * | 2009-10-29 | 2011-05-12 | Murata Mfg Co Ltd | Method of manufacturing ceramic substrate |
Also Published As
Publication number | Publication date |
---|---|
JPH0828579B2 (en) | 1996-03-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4753694A (en) | Process for forming multilayered ceramic substrate having solid metal conductors | |
US4806188A (en) | Method for fabricating multilayer circuits | |
EP2051570B1 (en) | Method of producing multilayer ceramic substrate | |
US4879156A (en) | Multilayered ceramic substrate having solid non-porous metal conductors | |
US5601672A (en) | Method for making ceramic substrates from thin and thick ceramic greensheets | |
KR100521941B1 (en) | Method of manufacturing a multi-layered ceramic substrate | |
KR20020070483A (en) | Method of manufacturing ceramic multi-layer substrate, and unbaked composite laminated body | |
JPH0697656A (en) | Production of ceramic multilayered board | |
US6562169B2 (en) | Multi-level web structure in use for thin sheet processing | |
US6488795B1 (en) | Multilayered ceramic substrate and method of producing the same | |
JPH0464281A (en) | Manufacture of ceramic multilayer board | |
EP1189495B1 (en) | Method of manufacturing multilayer ceramic substrate | |
JP2803414B2 (en) | Method for manufacturing multilayer ceramic substrate | |
JPH0983141A (en) | Method of manufacturing ceramic multi-layered substrate | |
JP2001144437A (en) | Multilayer ceramic board and method of production | |
JP3413880B2 (en) | Method for producing multilayer ceramic sintered body | |
JP4501227B2 (en) | Manufacturing method of ceramic multilayer wiring board | |
JP4196093B2 (en) | Manufacturing method of ceramic substrate | |
JPH0645757A (en) | Multilayer ceramic board and manufacture thereof | |
JP2002151855A (en) | Method of manufacturing multilayer ceramic board | |
JP2004095753A (en) | Method for manufacturing multi-layer ceramic substrate | |
JP2006005189A (en) | Ceramic substrate and its manufacturing method | |
KR20230120391A (en) | Multilayer ceramic substrate having an interlayer dummy and method of manufacturing the same | |
JPH10294561A (en) | Highly de-bindered multilayered wiring board and its manufacture | |
JP5055062B2 (en) | Wiring board manufacturing method and wiring board material |