JPS6364370A - Semiconductor phoetodtector - Google Patents
Semiconductor phoetodtectorInfo
- Publication number
- JPS6364370A JPS6364370A JP61208261A JP20826186A JPS6364370A JP S6364370 A JPS6364370 A JP S6364370A JP 61208261 A JP61208261 A JP 61208261A JP 20826186 A JP20826186 A JP 20826186A JP S6364370 A JPS6364370 A JP S6364370A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- controlling
- substrate
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 239000012535 impurity Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 13
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 3
- 230000003287 optical effect Effects 0.000 abstract description 2
- 238000010521 absorption reaction Methods 0.000 abstract 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- CVBNMWXECPZOLM-UHFFFAOYSA-N Rhamnetin Natural products COc1cc(O)c2C(=O)C(=C(Oc2c1)c3ccc(O)c(O)c3O)O CVBNMWXECPZOLM-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 101150002500 rhaM gene Proteins 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Landscapes
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、元ファイバを用いた光通信に使用される半導
体受光素子に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor light-receiving element used in optical communication using an original fiber.
従来から使用されていたPINホトダイオードは、合と
、小さい場合とで、出力電流に非常に大きな差が生じる
。通常この出力差は、 PINの後段に接続する増幅回
路の増幅率を可変とすることで対処している。In conventionally used PIN photodiodes, there is a very large difference in the output current between the small and large PIN photodiodes. Normally, this output difference is dealt with by making the amplification factor of the amplifier circuit connected after the PIN variable.
しかし、増幅回路のゲインの可変範囲が60dB村度必
要となり、電気回路の構成が、複雑になるという欠点が
あった。However, the variable range of the gain of the amplifier circuit needs to be 60 dB, and the configuration of the electric circuit becomes complicated.
本発明の目的は、外部印加電圧により、等価的に光/電
流変換効率を制御できる例えばPINホトダイオード等
の半導体受光素子を提供することにめるO
〔問題点を解決するだめの手段〕
本発明は、一方の導電型にドープされた第1の半導体ノ
ー上に、他方の尋′に型にドープされた第2の半導体ノ
ロを有し、その上に一方の導電型にドープされた第3の
半導体1゛Δを有し、その上に低不純物一度の一方の4
電型にドープされた第4の半導体層を有し、その上に1
聞不純物疑夏の他方の導電=:l IP+4
、Oン−? 4i+’+’ : rハM丘;、i
4升し; F# ii l r’L
+()半導体層の一部が、第1の半導体層に直接後し
ていること全特徴とするものである。An object of the present invention is to provide a semiconductor light receiving element, such as a PIN photodiode, whose light/current conversion efficiency can be equivalently controlled by an externally applied voltage. [Means for solving the problems] The present invention has a first semiconductor layer doped with one conductivity type, a second semiconductor layer doped with the other conductivity type, and a third semiconductor layer doped with one conductivity type thereon. The semiconductor has a 1゛Δ of
a fourth doped semiconductor layer;
The other conductivity of impurities and summer =:l IP+4
, Oon-? 4i+'+': rhaM hill;,i
4 sho; F# ii l r'L
+() A part of the semiconductor layer is directly behind the first semiconductor layer.
本発明は、外部印加電圧によシ光吸収層である第4層内
でかつ、基板である第1層近傍に形成される空乏層を制
御し、 PINホトダイオードに流れる電流のうち、基
板側にバイパスする電流量全制御することにより、等測
的な光/電流変換効率を可変とすることを最も主要な特
徴とする。The present invention controls the depletion layer formed in the fourth layer, which is the light absorption layer, and near the first layer, which is the substrate, by an externally applied voltage, and controls the current flowing through the PIN photodiode toward the substrate side. The most important feature is that the isometric light/current conversion efficiency is made variable by fully controlling the amount of bypassed current.
第1図は、本発明の第1の実施例を説明する図であって
、1は−(p+)型InP基板、11はn(p)ffl
InPバッファ層、2はp (n)型InP層、3はn
(p)型InGaAsP層、4はn−(p−)型I
nGaAa層、5はInGaAs層にイオン打ち込みに
より構成したp”(n”)型InGaAs層、6は層5
とオーミックな電極、7はプラズマCVD法又は、 E
CR法で作製した絶碌のためのS 13N4層、8は空
乏層制御用逆バイアス電源(V2)19は3,4.5層
で形成されるPINホトダイオード用逆バイアス電源(
Vl )、10は空乏層、11は半導体層5の周囲の電
界強度全低減する念めに、イオン注入法によるCd注入
等で作らnたガードリング、12は信号検出用の負荷抵
抗である。FIG. 1 is a diagram for explaining the first embodiment of the present invention, in which 1 is a −(p+) type InP substrate, 11 is an n(p)ffl
InP buffer layer, 2 is p (n) type InP layer, 3 is n
(p) type InGaAsP layer, 4 is n-(p-) type I
nGaAa layer, 5 is a p"(n") type InGaAs layer formed by ion implantation into the InGaAs layer, 6 is layer 5
and ohmic electrode, 7 is plasma CVD method or E
4 S 13N layers for high performance fabricated by CR method, 8 is a reverse bias power supply (V2) for controlling the depletion layer, 19 is a reverse bias power supply for PIN photodiode formed by 3, 4.5 layers (
Vl), 10 is a depletion layer, 11 is a guard ring made by Cd implantation using an ion implantation method in order to completely reduce the electric field strength around the semiconductor layer 5, and 12 is a load resistor for signal detection.
なお、基板12層1,2〜5中の0内はp型基板上に作
製した場合を示す。Note that 0 in layers 1, 2 to 5 of the substrate 12 indicates the case where the layers were fabricated on a p-type substrate.
第1図中、工11工2pI3は一流を懺イクす。In Figure 1, Engineering 11 Engineering 2pI3 is top notch.
次に本素子の基本動作について説明する。Next, the basic operation of this device will be explained.
本素子の機能は、大別すると2つの機能に分れる。The functions of this element can be roughly divided into two functions.
第1の機能は、第1図中の半導体層3,415よシ構成
されるPINホトダイオードによる光/電流変換機能、
第2の機能は第1図中の半導体層1′。The first function is a light/current conversion function by a PIN photodiode constructed from the semiconductor layer 3,415 in FIG.
The second function is the semiconductor layer 1' in FIG.
2.4から構成されるPNノヤンクンヨンへの逆バイア
ス印加により層4内に形成される空乏層10’f、印加
電圧によ多制御することによp、PINホトダイオード
にて光/・直流変換された電流の基板1への流入量を制
御する機能である。The depletion layer 10'f formed in the layer 4 by applying a reverse bias to the PN layer 4 composed of 2.4 is photo/DC converted by the PIN photodiode by controlling the applied voltage. This function controls the amount of current flowing into the substrate 1.
第1図において、半導体層5但1よシ入射した光は、半
導体層4内で吸収され、正孔及び電子全発生する。これ
らの正孔、電子は、層4内の電界によシトリフトし、電
子は基板1及び半導体層3へ、正孔は半導体層5へ流入
しs 工t =’2 + Isとなる電流が流れる。In FIG. 1, light incident on the semiconductor layer 5 is absorbed within the semiconductor layer 4, and all holes and electrons are generated. These holes and electrons are lifted by the electric field in the layer 4, the electrons flow into the substrate 1 and the semiconductor layer 3, the holes flow into the semiconductor layer 5, and a current flows such that s t ='2 + Is .
一方、本素子は、V、を制御することにより空乏J−1
0の領域を制御できる。On the other hand, in this device, by controlling V, the depletion J-1
0 area can be controlled.
したがって基板1に流入する電子によって生じる工3の
大きさを制御できる。その結果、受光信号電流として使
用する工2の電流値を制御できる。Therefore, the size of the crack 3 caused by the electrons flowing into the substrate 1 can be controlled. As a result, the current value of the circuit 2 used as the light reception signal current can be controlled.
木調(子の主要な構造パラメータ例を第1表に示す。Table 1 shows examples of the main structural parameters of wood grains.
以上説明したように、本発明は外部印加電圧により信号
電流の大きさを制御できるので、光フアイバ通信用の受
光回路として用いた場合、方式上要求される最大及び最
小受光電力時の信号電流値の比を小さくできる。したが
って受光素子の次段以後に接続される増幅回路のAGC
(自動利得制御)の所要グイナミックレンソを小さくで
きるという利点がある。As explained above, since the present invention can control the magnitude of the signal current by externally applied voltage, when used as a light receiving circuit for optical fiber communication, the signal current value at the maximum and minimum light receiving power required by the method The ratio of can be reduced. Therefore, the AGC of the amplifier circuit connected after the next stage of the light receiving element
This has the advantage that the required magnitude for automatic gain control (automatic gain control) can be reduced.
第1図は本発明の第1の実施例の断面図である。
1− n (p )InP基板、1’−・n (p)型
1nPバッファ層、2 ・・・p(n)型InP層、3
−”nφ)W InGaAsP r=、4−=n−(p
−″)型InGaAs層、5 =−p (n−)型1n
GaAs f’3゜6・・・J運5とオーミックな電極
、7・・・絶僅のためのSi、N4層、8・・・空乏層
制御用逆バイアス電源、9・・・PINホトダイオード
用逆バイアス電源、10・・・空乏層、11・・・ガー
ドリング、12・・・負荷抵抗、0内はp型基板の場合
である。FIG. 1 is a sectional view of a first embodiment of the invention. 1-n(p) InP substrate, 1'-n(p) type 1nP buffer layer, 2...p(n) type InP layer, 3
-”nφ)W InGaAsP r=,4-=n-(p
-'') type InGaAs layer, 5 = -p (n-) type 1n
GaAs f'3゜6... J connection 5 and ohmic electrode, 7... Si, N4 layer for extremely low density, 8... Reverse bias power supply for depletion layer control, 9... For PIN photodiode Reverse bias power supply, 10... depletion layer, 11... guard ring, 12... load resistance, 0 indicates the case of a p-type substrate.
Claims (1)
の導電型にドープされた第2の半導体層を有し、その上
に一方の導電型にドープされた第3の半導体層を有し、
その上に低不純物濃度の一方の導電型にドープされた第
4の半導体層を有し、その上に高不純物濃度の他方の導
電型にドープされた第5の半導体層を有し、第4の半導
体層の一部が、第1の半導体層に直接接していることを
特徴とする半導体受光素子。A first semiconductor layer doped with one conductivity type has a second semiconductor layer doped with the other conductivity type, and a third semiconductor layer doped with one conductivity type is formed on top of the second semiconductor layer doped with the other conductivity type. have,
a fourth semiconductor layer doped with one conductivity type with a low impurity concentration thereon; a fifth semiconductor layer doped with the other conductivity type with a high impurity concentration thereon; A semiconductor light-receiving element, wherein a part of the semiconductor layer is in direct contact with a first semiconductor layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61208261A JPS6364370A (en) | 1986-09-04 | 1986-09-04 | Semiconductor phoetodtector |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61208261A JPS6364370A (en) | 1986-09-04 | 1986-09-04 | Semiconductor phoetodtector |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6364370A true JPS6364370A (en) | 1988-03-22 |
Family
ID=16553308
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61208261A Pending JPS6364370A (en) | 1986-09-04 | 1986-09-04 | Semiconductor phoetodtector |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6364370A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0490015A (en) * | 1990-08-02 | 1992-03-24 | Mitsubishi Electric Corp | Optical neurocomputer |
JP2008016535A (en) * | 2006-07-04 | 2008-01-24 | Opnext Japan Inc | Surface-incident light receiving element and light-receiving module |
-
1986
- 1986-09-04 JP JP61208261A patent/JPS6364370A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0490015A (en) * | 1990-08-02 | 1992-03-24 | Mitsubishi Electric Corp | Optical neurocomputer |
JP2008016535A (en) * | 2006-07-04 | 2008-01-24 | Opnext Japan Inc | Surface-incident light receiving element and light-receiving module |
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