JPS6363135B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a phase locked loop circuit (hereinafter referred to as a PLL circuit), and its purpose is to add a reset circuit to a conventional PLL circuit to expand the frequency pull-in range. It is in.

There is no original bit clock component in the signal itself, such as 3PM code or EFM code, and the original bit clock is restored from a signal consisting only of signals with pulse widths from 3 times to 11 times that of the original bit clock component. Conventionally, as a means, PLL as shown in Figure 1 is used.
circuit is used. To explain the operation of this circuit using FIG. 2, the edge detector 1 detects the edge of the input signal S and outputs a pulse G of a constant width, and this pulse G connects the switch circuit 2 to control the voltage. The output of the oscillator 4 or the divided output CK is passed through the frequency divider 5, and the clock PD thus extracted is integrated by the integrating circuit 3, and the logic level of the extracted clock is "H". A control voltage VC proportional to the ratio of the period to the "L" period is obtained, and the oscillation frequency of the voltage controlled oscillator 4 follows the frequency of the input signal S by this control voltage VC.

However, in such a phase comparison method using a switch, if the oscillation frequency of the voltage controlled oscillator 4 is not close to the clock frequency of the input signal S, an erroneous phase comparison output will be generated and pull-in will not be possible. An example is shown in FIG. In the first edge detection pulse _G1 ,
The clock phase is in the correct position and the integrator circuit 3
The "H" and "L" periods of the phase comparison output PD are canceled and the control voltage VC does not move, but the "H" period of the second edge detection pulse _G2 is long, and conversely, the third edge detection pulse In pulse _G3 , the "L" period is long, and the control voltage moves in the opposite direction, making it impossible to perform correct frequency control.

The frequency pull-in range of this PLL circuit is determined by the input signal. As shown in FIG. 4, among the edge detection pulses G, those shown by solid lines are when the synchronization is completely achieved, and "H" and "L" of the phase comparison output PD are canceled. When the frequency of the input signal S is low, the edge detection pulse G moves toward the one shown by the broken line. Therefore, the phase comparison output
PD has a large "L" component, which works to lower the frequency of the voltage controlled oscillator 4 to ensure proper control. However, if the frequency is lower than the position indicated by the broken line, the phase comparison output PD will be “H”.
The number of components increases, and the frequency of the voltage controlled oscillator 4 tries to rise, but cannot be pulled down. Here, if the width of one clock is T, then the pull-in range can be expressed as 0.5T/Tmin, where Tmin is the minimum pulse width of the input signal. The same applies when the frequency of the input signal S is high. Therefore, the retractable range is ±0.5T/Tmin. In the case of 3PM code and EFM code, Tmin = 3T, so the range that can be pulled in is ±0.5T/3T = ±16.7 [%]. In reality, there is a signal with a long pulse width other than Tmin in the input signal S, and the phase comparison output PD in that case may generate an erroneous control voltage. Therefore, in order to obtain only a completely correct phase comparison output PD, it is necessary to limit the pull-in range to ±0.5T/Tmax, where Tmax is the maximum pulse width of the input signal. In the case of the EFM code, Tmax = 11T, so the pull-in range is ±0.5T/11T = 4.5 [%], and frequency pull-in can only be performed within a very narrow range.

Therefore, the present invention provides an edge detector that detects the edge of an input signal and generates a pulse of a constant width, and a switch circuit that intermittents the output of a voltage controlled oscillator or its frequency-divided output using the output pulse of this edge detector. The input threshold voltage is set to be slightly shifted from the center of the high level and low level voltages of the output of this switch circuit, and an integrating circuit is provided to integrate the output of this switch circuit, and the output voltage of this integrating circuit is set to be the voltage of the above voltage. By providing a reset circuit that supplies the edge detection pulse as a control voltage to the controlled oscillator and detects that the output voltage of the integration circuit exceeds a predetermined value and stops the edge detection pulse for a certain period of time, the pull-in range can be adjusted. is expanded arbitrarily. Hereinafter, the present invention will be explained based on examples.

When the switch circuit 2 of FIG. 1 is off, the input voltage of the integrating circuit 3 is determined by the input threshold voltage of the integrating circuit 3. Normally, this threshold voltage is used as the “H” and “L” of the phase comparison output PD.
However, in the PLL circuit of the present invention, the voltage is set slightly off from the center. Therefore, as shown in Fig. 5, the phase comparison output PD is
"H" and "L" have different amplitudes, and even if the "H" and "L" periods are equal, the control voltage after integration will deviate slightly to the higher or lower side.

When the PLL circuit is not locked, the sum of the "H" periods and the sum of the "L" periods of the phase comparison output PD are approximately equal in the long run. Therefore, the control voltage VC gradually moves higher or lower in accordance with the difference in amplitude between "H" and "L" of the phase comparison output PD. When the voltage falls within the above-mentioned pull-in range, the correct control voltage is generated and the pull-in occurs rapidly. However, once the pull-in fails, the control voltage is stuck at "H" or "L" and does not move. Therefore, in FIG. 6 showing an embodiment of the present invention, a reset circuit 6 monitors the output voltage VC of the integrating circuit 3 and, when the voltage exceeds a predetermined voltage, stops the edge detection pulse G and resets the PLL. It is provided.

A specific example of the reset circuit 6 is shown in FIGS. 7 and 8.

In the example of FIG. 7, the input voltage VC is set to a predetermined voltage V _S1 by the voltage comparator 61 as shown in FIG.
The reset pulse generator 62 is operated based on the output CR. The reset pulse generator 62 repeatedly generates a reset pulse R of a predetermined width. Normally, when the first reset pulse has been generated, the input voltage has returned to its normal value, so the output CR of the voltage comparator 61 is stopped, and the second and subsequent reset pulses R are not generated. If the input voltage does not return to normal, a reset pulse R will be generated repeatedly. This reset pulse generator 62 can be easily realized using a multivibrator or the like. The width of the reset pulse R is preset to the time it takes for the input voltage VC to reach a predetermined value _VS2 .

In the example shown in FIG. 8, voltage comparators 63 and 64 are used, and when one voltage comparator 63 detects that the input voltage VC exceeds the threshold voltage _VS1 , the flip-flop 65 is reset. Flip-flop 65 outputs a reset pulse R as soon as it is set. When the input voltage VC exceeds the threshold voltage _VS2 , the voltage comparator 64 resets the flip-flop 65 and stops the reset pulse R. The reset pulse may be generated by controlling the edge detector 1 so as not to generate the edge detection pulse R, or by gating the edge detection pulse G to stop it.

To shorten the reset time, as shown in Figure 10, a switch 31 is provided between one end of the capacitor C of the integrating circuit 3 and the ground, and if configured to be turned on during the reset period, the charge in the capacitor will be rapidly discharged. This makes it possible to reset in a short time.

As explained above, according to the PLL circuit of the present invention, the oscillation frequency range of the voltage controlled oscillator can be expanded beyond the pull-in range without requiring a special automatic frequency control circuit by simply adding a reset circuit. It becomes possible to draw in. Therefore, it is extremely effective when reproducing a clock from a signal that does not contain a clock frequency component and has a large allowable bit rate range, such as a 3PM code recorded on a magnetic tape or an EFM code recorded on a disk at a constant linear velocity. It is something.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional PLL circuit.
2, 3, and 4 are signal waveform diagrams for explaining the operation of FIG. 1, FIGS. 5 to 10 show an embodiment of the present invention, and FIG. 5 is a signal waveform diagram for explaining the operation of the PLL. waveform diagram,
FIG. 6 is a block diagram of the PLL circuit of the present invention.
7, 8, and 10 are detailed configuration diagrams of the main parts of FIG. 6, and FIG. 9 is a waveform diagram for explaining the operation of FIG. 7. 3...Integrator circuit, 6...Reset circuit, 31...
...Switch circuit, 61, 63, 64... Voltage comparator, 62, 65... Reset pulse generator.

Claims (1)

[Scope of Claims] 1. An edge detector that detects edges of an input signal and generates pulses of a constant width, and a switch circuit that intermittents the output of a voltage controlled oscillator or its frequency-divided output based on the output pulse of this edge detector. The input threshold voltage is set to be slightly shifted from the center of the high level and low level voltages of the output of this switch circuit, and an integrating circuit is provided to integrate the output of this switch circuit, and the output voltage of this integrating circuit is a reset circuit that supplies the voltage-controlled oscillator as a control voltage and detects that the output voltage of the integrating circuit exceeds a predetermined value and stops the operation of the edge detector for a certain period of time. - Locked loop circuit. 2. The reset circuit is configured to detect that the output voltage of the integrating circuit exceeds a predetermined value, stop the edge detection pulse for a certain period of time, and simultaneously discharge the charge in the integrating circuit. Phase locked loop circuit according to item 1. 3. The reset circuit starts resetting the edge detection pulse when it detects that the output voltage of the integrating circuit exceeds the first set voltage, and cancels the reset of the edge detection pulse when the output voltage exceeds the second set voltage. A phase locked loop circuit according to claim 1, constructed as described above. 4. The reset circuit starts resetting the edge detection pulse when it detects that the output voltage of the integrating circuit exceeds the first set voltage, and releases the reset of the edge detection pulse when the output voltage exceeds the second set voltage. 2. A phase locked loop circuit according to claim 1, comprising a first reset means and a second reset means for discharging the charge of the integrating circuit.