JP3367381B2 - Phase locked loop circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked loop (hereinafter referred to as PLL) for recovering a clock signal from an input signal.
Circuit), and more particularly to a phase locked loop circuit including a frequency comparator that detects a frequency deviation between an input signal and a recovered clock signal.

[0002]

2. Description of the Related Art A PLL circuit is configured to control a VCO (voltage controlled oscillator) on the basis of the result of phase comparison between an input signal and a reproduced clock signal. Therefore, if the frequency variable range is widened, there is a problem that side lock is likely to occur. For example, EFM (Eight-Four) of a CD player
In the case of a teen modulation signal, a pattern of 3T to 11T (T is a reference cycle) is used, but when there is no signal, a relatively simple pattern is repeated with a specific cycle, for example, 34T as one cycle. In this case, if the reproduced clock is settled in the period of 34T for exactly 33 periods or 35 periods, the phase difference output also repeats 34T periods, and L
The DC component of the phase difference output that has passed through the PF (low-pass filter) becomes 0, and the side lock state occurs.

Therefore, in order to prevent side lock while keeping the variable frequency range of the VCO wide, a PLL circuit using a frequency comparator together with a phase comparator has been conventionally used. In such a PLL circuit, the frequency comparator counts the edge interval of the EFM signal and detects the frequency deviation between the input signal and the reproduction clock from the count value. For example, when the maximum inversion width of 11T is counted by the VCO clock, if the count value is 10.5T or less, the output frequency of the VCO is increased, and if it is 11.5T or more, the output frequency of the VCO is decreased. Control the oscillation frequency of the VCO.

By the way, as shown in FIG. 5, the frequency comparator outputs the maximum inversion width 11T of the EFM signal to the reproduction clock CK.
If the cycle of the reproduction clock CK corresponds to the reference cycle T of the EFM signal, a pulse having a length of 11T is counted by the reproduction clock CK for 11 cycles, as shown in FIG. However, as shown by the dotted line in the figure, when the reproduction clock CK is used as a reference, the pulse width of the EFM signal is 1 from 10T to 12T.
It may be counted as 1T. This range is the dead zone of the frequency comparator. Further, as shown in FIG. 7B, if the frequency of the reproduction clock CK is doubled and the maximum inversion width 11T of the EFM signal is set to count 22 cycles with the reproduction clock CK, it is indicated by a dotted line in the figure. Thus, the dead band of the frequency comparator is narrower than in the previous example.

[0005]

As described above, in the PLL circuit using the frequency comparator, the dead band always exists in the frequency comparator, and in order to narrow the dead band, a high frequency clock signal or high accuracy is required. Requires an analog delay line. Further, since EFM signals such as CD, MD, and DAT always include jitter, if the dead zone is made too narrow, it will be erroneously V
There is a problem that the control signal of CO is frequently output and the feedback loop oscillates across the dead zone.
On the other hand, if the dead band of the frequency comparator is widened, there is a frequency point where side lock is likely to occur in the dead band, and the side lock state continues for a long time, it takes time to pull in, or in the worst case, the synchronization state. There was also the problem of not reaching.

The present invention has been made in view of the above problems, and even if the dead band of the frequency deviation absorbing means is set to be slightly wide, the side lock state does not continue for a long time and is required for true synchronization. An object of the present invention is to provide a phase locked loop circuit that can shorten the time.

[0007]

SUMMARY OF THE INVENTION The present invention includes a phase comparator for detecting a phase difference between an input signal and a recovered clock signal,
A loop filter for filtering the phase difference detected by the phase comparator, a control oscillator whose frequency is controlled based on the output of the loop filter to output the reproduction clock signal, and a reproduction clock output from the control oscillator. In order to absorb the detected frequency deviation, the edge interval of the input signal is counted based on the signal, the frequency deviation between the input signal and the reproduction clock is detected when the count value is outside a predetermined range. In a phase-locked loop circuit including frequency deviation absorbing means for controlling the frequency of the controlled oscillator, a true lock is made based on a cycle longer than the frequency deviation detecting operation in the frequency deviation absorbing means after the pull-in operation is started. Lock detection means for detecting that the state has been reached, and this lock detection means Side lock preventing means for controlling the frequency of the controlled oscillator to be forcibly changed in either direction when the frequency deviation is not detected for a certain time without detecting the locked state of To do.

According to the present invention, when the lock detecting means does not detect that the lock state is the true lock state after the pull-in operation is started and the frequency deviation is not continuously detected for a certain period of time, the side lock state is set. Since it is determined that there is such a situation, the frequency is changed by forcibly controlling the controlled oscillator, so that even if the side-lock state is entered, it is possible to get out of this state after a certain period of time. For this reason, even if the dead band of the frequency deviation absorbing means is set to be wide so as to include the side lock frequency, it is necessary to prevent the state from continuing for a long time and control the control oscillator so that the true lock state is achieved in a short time. Will be possible.

The side lock preventing means includes, for example, a pull-in direction storing means for storing a pull-in direction indicating whether the frequency is rising or falling during pull-in operation, and a state in which the frequency deviation absorbing means does not detect the frequency deviation. a timer for detecting that a predetermined period has continued, the timer is pre
After detecting that the state of not detecting a frequency deviation continues <br/> predetermined time serial frequency deviation absorbing means, forced to change to the stored retraction direction retraction direction storage means the frequency of the controlled oscillator Control means for controlling the According to such a configuration, when the system is pulled out of the side lock, the pulling direction stored in the pulling direction storage means, that is, based on the information indicating whether the frequency is rising or falling, is appropriate. Since the controlled oscillator can be controlled in any direction, the time required for true synchronization can be further shortened.

Further, the lock detecting means establishes a true lock state when, for example, a synchronizing signal generated for each frame period of the input signal and a pulse of a period corresponding to the frame period generated from the reproduction clock are synchronized. It may be configured to detect.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing the configuration of a phase locked loop circuit according to an embodiment of the present invention. The EFM signal, which is an input signal, is input to the inversion interval detection unit 1, where it is detected what the edge interval of the EFM pulse is, with the cycle T of the reproduction clock CK as a unit. The counter 3 counts the reproduction clock signal CK output from the VCO 2, generates a pulse SCK every N cycles of the reproduction clock CK, and outputs the pulse SCK.
The frequency comparator 4 and the lock detection circuit 12 to be described later
It is used as the reference signal of. Here, the value of N is set to 588, for example, corresponding to the frame period of the EFM signal, as described later. The inversion interval detection unit 1 generates a count pulse from the reference signal SCK and counts the inversion interval of the EFM signal. EFM signal is 3T-11T
Up to 10.5.
A signal indicating that a pulse having a width of T or more, a pulse having a width of 11.5T or more, and a pulse having a width of 11T has been detected is output.

When the frequency comparator 4 does not detect a pulse having a width of 10.5T or more from the inversion interval detector 1 within a predetermined period, the frequency of the input EFM signal is VC.
When it is determined that the frequency is higher than the output frequency of O2, the up-trigger signal FUS for increasing the frequency of VCO2 is output, and when a pulse having a width of 11.5T or more is detected during the above-mentioned fixed period, the input EFM signal It is determined that the frequency is lower than the output frequency of VCO2, and the down trigger signal FDS for lowering the frequency of VCO2 is output. These trigger signals FUS and FDS are given to the one-shot circuit 7 via the OR gates 5 and 6, respectively. The one-shot circuit 7 uses the trigger signals FUS and FDS as a trigger to output an up pulse FUP and a down pulse FDW having a constant pulse width longer than the trigger signals FUS and FDS from the Q output terminals, respectively. Charge pump 8
Outputs an "H" level signal when an up pulse FUP is input from the one-shot circuit 7 and outputs an "L" level signal when a down pulse FDW is input, and when neither of them is input. The output becomes high impedance. The inversion interval detector 1, the frequency comparator 4, the one-shot circuit 7 and the charge pump 8 constitute a frequency deviation absorbing means.

On the other hand, the input EFM signal and the reproduced clock signal CK from the VCO 2 are input to the phase comparator 9 and the phase difference between them is detected. The phase difference and the output of the charge pump 8 are given to the loop filter 10, the control voltage VC based on the phase difference and the frequency deviation is fed back to VCO2, and the output frequency of VCO2 is controlled.

Further, in this circuit, in order to prevent side lock, the side lock prevention circuit 11 and the lock detector 1 are provided.
2 and are provided. The side lock prevention circuit 11
The UP register 21 and the DO as the pull-in direction storage means
It comprises a WN register 22, a timer 23, a decoder 24 as control means, and OR gates 25, 26 and 27. The UP register 21 is a register for storing that the pulling operation of the VCO 2 is performed in the direction of increasing the frequency, and is set by the up trigger signal FUS from the frequency comparator 4, and the output of the OR gate 25,
That is, it is reset by the down trigger signal FDS from the frequency comparator 4, and is held in the reset state while the lock detection unit 12 detects the locked state. The DOWN register 22 is a register for storing that the pulling operation of the VCO 2 is performed in the direction of decreasing the frequency,
The output of the OR gate 26 is set by the down-trigger signal FDS from the frequency comparator 4, that is, the frequency comparator 4
Is reset by the up trigger signal FUS from
While the lock detector 12 detects the lock state, the lock state is held in the reset state. The timer 23 does not operate when locked and always counts up except when reset by the trigger signals FUS and FDS. When it reaches a certain value, it outputs a pulse to the decoder 24, resets itself at the same time, and starts counting again. As a result, it is detected that the trigger signals FUS and FDS have not been generated within a certain fixed time. When the pulse is input from the timer 23, the decoder 24 outputs the up trigger signal FUST or the down trigger signal FDST to the one-shot circuit 7 based on the outputs of the registers 21 and 22.

The lock detector 12 is provided to detect the true lock state and bring the side lock detection circuit 11 into a non-operating state. In this embodiment, the true lock state is detected as follows. That is, taking a music CD as an example, as shown in FIG. 2, the EFM signal has a total of 32 words including 12 words of data, 4 words of Q parity, 12 words of data and 4 words of P parity. One frame is formed by adding a synchronization signal SYNC to the head of data. This one frame has a period of 588T. Therefore, the cycle N of the counter 3 is set to 588,
The reference signal SCK is output from the counter 3 every 588 cycles of the reproduction clock CK. On the other hand, since the SYNC pattern includes 11T pulses, the lock detection unit 11 outputs the 11T pulses output from the inversion interval detection unit 1.
SYNC signal is detected from the signal pattern of
The true lock state is detected when the C signal is synchronized with the reference signal SCK output from the counter 3.

Next, the operation of the phase-locked loop circuit configured as above will be described. FIG. 3 is a graph showing the relationship between the output frequency of the VCO 2 and the occurrence probabilities of the up pulse FUP and the down pulse FDW. Now, assuming that the specified frequency of the EFM signal is 4.3218 MHz, the frequency of VCO2 that detects that the 11T pulse of the EFM signal is 10.5T or less is 95.5% of the specified frequency.
(= 10.5T / 11T), that is, a frequency of 4.125 MHz or less, and the frequency of VCO2 that detects a 11T pulse to be 11.5T or more is 104.5% (= 11. 5T / 11T), or 4.51
The frequency is 8 MHz or higher. Actually, due to the positional relationship between the 11T pulse edge and the rising edge of the VCO2 output pulse CK, the probability of outputting the up pulse FUP gradually increases from -4.5% to almost 100 at -9%. % Up pulse FUP is output. Similarly, the probability of outputting the down pulse FDW gradually increases from + 4.5%, and at + 9%, the down pulse FDW is almost 100%.
Is output. The dead zone of the frequency comparator 4 is between them.

On the other hand, as described above, the period of 34T is 3
Side lock easily occurs when 3T or 35T is entered. The frequency of VCO2 at that time is 4.198 MHz
(= 4.3218 MHz × 34T / 35T) and 4.4
53MHz (= 4.3218MHz x 34T / 33T)
Is. Since these frequencies fall within the dead zone region of FIG. 3, when the side lock is performed at these frequencies, the state in which neither the up pulse FUP nor the down pulse FDW is output continues. The side lock prevention circuit 11 detects that such a state has continued for a certain period of time, forcibly outputs the up pulse FUP and the down pulse FDW, and operates to get out of the side lock state.

That is, assuming that the pull-in is started from the state where the frequency of VCO2 is lower than the frequency of the EFM signal, the frequency comparator 4 judges that the frequency of VCO2 is low, as shown in FIG. Output FUS. Then, the up pulse FUP is output from the one-shot circuit 7 using the signal FUS as a trigger, and the capacitance C of the loop filter 10 is charged through the charge pump 8. Therefore, the control voltage VC output from the loop filter 10 is illustrated. To rise. This operation is VCO2
Is repeated until the frequency of reaches the dead band of the frequency comparator 4. When the frequency of VCO2 reaches the dead band, the up pulse FUP is no longer output. During this period, the frequency of the VCO 2 is controlled based on the output of the phase comparator 9.

If the side lock state is reached here, and the side lock prevention circuit 11 is not provided, as shown in FIG.
As shown in (a), the control voltage VC remains constant, but according to the circuit of this embodiment, the timer 23 is not reset as shown in (b) of the figure. Since the count-up is continued up to a fixed value, a pulse is applied to the decoder 24 after a fixed time has elapsed. Prior to this, the up trigger signal FUS is VCO2.
The timer 23 is reset at the same time as the UP register 21 which stores that the pull-in operation is being performed in the direction of increasing the frequency is set. As a result, the decoder 24 outputs the up-trigger signal FUST because the UP register 21 is in the set state, and the one-shot circuit 7 outputs the up-pulse FUP to output VC.
O2 will come out of the side lock state. Further, even when the pull-in is started from the state where the frequency of the VCO 2 is higher than the frequency of the EFM signal, the down pulse FDW is output by the same operation. And VCO
When the frequency of 2 reaches the specified frequency, the lock detector 1
2 detects this, registers 21, 22 and timer 23
Is always reset to prohibit the output of the forced pulse.

According to this embodiment, the up pulse FUP is output when the frequency of the VCO 2 is rising before falling into the side lock state, and the down pulse FDP is output when it is falling. When neither of them is output, either of the pulses is output to change the frequency of the VCO2, so that the VC is moved in the appropriate direction.
The frequency of O2 can be changed, and the time required for synchronization can be greatly reduced.

The present invention is not limited to the control mode of the VCO 2 described above, and the VC can be controlled in either the ascending direction or the descending direction regardless of the immediately preceding control direction.
The frequency of O2 may be changed. In this case, the frequency may fluctuate in the direction opposite to the direction toward the specified frequency, but rather than maintaining the side lock state,
The time taken to get out of the process and re-synchronize can be overwhelmingly shortened.

[0022]

As described above, according to the present invention,
If the lock detector does not detect that the lock state has been true since the pull-in operation started, and if the frequency deviation is not detected for a certain period of time, it is determined to be the side-lock state and the control oscillator is forced. The frequency is controlled by changing the frequency, so that even if the user has fallen into the side lock state, it is possible to get out of this state after a certain period of time, and the dead band of the frequency deviation absorbing means is removed from the side lock frequency. Even if it is widely set so as to include, it is possible to prevent the state from continuing for a long time and control the controlled oscillator so as to be in the true lock state in a short time.

[Brief description of drawings]

FIG. 1 is a block diagram of a phase locked loop circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a frame configuration example of an EFM signal input to the same circuit.

FIG. 3 is a graph showing the relationship between the VCO frequency and the up / down pulse occurrence probability in the same circuit.

FIG. 4 is a time chart for explaining the operation of the circuit.

FIG. 5 is a diagram for explaining a dead zone of a phase locked loop circuit including a frequency comparator.

[Explanation of symbols]

1 ... Inversion interval detector, 2 ... VCO (voltage controlled oscillator),
3 ... Counter, 4 ... Frequency comparator, 7 ... One-shot circuit, 8 ... Charge pump, 9 ... Phase comparator, 10 ... Loop filter, 11 ... Side lock prevention circuit, 12 ... Lock detector.

Claims (3)

(57) [Claims] 1. A phase comparator for detecting a phase difference between an input signal and a recovered clock signal, a loop filter for filtering the phase difference detected by the phase comparator, and a frequency based on the output of the loop filter. A controlled oscillator which outputs the reproduced clock signal controlled by the control oscillator, counts the edge interval of the input signal based on the reproduced clock signal output from the controlled oscillator, and determines that the count value is outside a predetermined range. In the phase locked loop circuit including the frequency deviation absorbing means for detecting the frequency deviation between the input signal and the reproduction clock and controlling the frequency of the controlled oscillator to absorb the detected frequency deviation, the pull-in operation is started. After that, based on a cycle longer than the frequency deviation detecting operation in the frequency deviation absorbing means, Lock detecting means for detecting that the lock state is in a true lock state, and when the frequency deviation is not detected for a certain period of time without the lock detecting means detecting the true lock state, the frequency of the controlled oscillator is set in either direction. And a side lock prevention means for controlling so as to forcibly change the phase lock loop circuit. 2. The side lock prevention means stores a pulling direction indicating whether the frequency is rising or falling during pulling operation, and the frequency deviation absorbing means detects a frequency deviation. A timer that detects that a state in which the frequency deviation is not maintained has continued for a certain period of time, and this timer uses the frequency deviation absorbing means to detect the frequency deviation.
If it detects that the undetected state has continued for a certain period of time,
2. The phase-locked loop circuit according to claim 1, further comprising control means for forcibly controlling the frequency of the controlled oscillator to change in the pull-in direction stored in the pull-in direction storage means. 3. The lock detecting means is in a true lock state when a synchronization signal generated every frame period of the input signal and a pulse of a period corresponding to the frame period generated from the reproduction clock are synchronized. The phase-locked loop circuit according to claim 1 or 2, wherein